SATA 2.6协议手册：Serial ATA International Organization发布的重要参考

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Serial ATA Revision 2.6是由Serial ATA International Organization（简称SATAnext）制定的一项关键的存储接口标准，该文档于2007年2月发布。此版本的协议手册旨在提供高速、串行化的数据传输机制，以提升硬盘驱动器（HDD）和固态硬盘（SSD）等存储设备的性能和连接性。它覆盖了Serial ATA的基础原理、命令集、规范细节及其实现要点，对深入理解SATA技术的学习者来说非常有价值。 SATA 2.6规范主要关注以下几个方面： 1. **标准化与一致性**：SATAnext作为国际组织，确保了协议的一致性和兼容性，使得不同厂商生产的SATA设备能在全球范围内顺畅交互，减少了系统集成时的复杂性。 2. **高数据传输速度**：与早期版本相比，SATA 2.6显著提升了数据传输速率，这得益于更快的信号传输速度和更有效的总线设计，从而提高了存储设备的读写效率。 3. **板级支持附件（B SATA）**：这份规格详细定义了如何在主板上实现SATA接口，包括物理连接、电源管理和信号处理，确保硬件工程师能够按照标准进行设计。 4. **命令集与功能**：手册中包含了丰富的SATA命令集，如寻道操作、错误检测、数据传输和管理等，这些都是驱动程序和硬件交互的核心要素。 5. **无保证条款**：尽管提供了规范，但SATAnext强调这份文档“按原样”提供，并不包含任何形式的保修或保证，使用者需自行承担可能的侵权风险和适配特定用途的责任。这意味着开发者在使用这些信息时，需要自行评估其法律风险。 6. **获取资源**：有兴趣的读者可以从www.sata-io.org网站下载SATA 2.6的最终规格，以便查阅最新的规范内容。 Serial ATA Revision 2.6是一个重要的技术参考文献，对于了解和开发基于SATA的存储解决方案的工程师、硬件制造商以及系统集成商来说，理解和掌握其中的内容是至关重要的。它不仅规范了硬件接口，还推动了存储技术的进步，对于现代计算机系统的性能优化起到了关键作用。

Figure 217 – Device Activity LEDs with Separate Wires............................................................. 493

Figure 218 – Device Activity LEDs with Ribbon Cable................................................................ 494

Figure 219 – Device Activity LEDs in a Storage Subsystem....................................................... 495

Figure 220 – Software reset to control port result values............................................................ 496

Figure 221 – Port Multiplier Signature ......................................................................................... 498

Figure 222 – SActive register definition....................................................................................... 504

Figure 223 – SNotification register definition............................................................................... 505

Figure 224 – Error handling architecture..................................................................................... 507

Figure 225 – Port Multiplier Overview ......................................................................................... 517

Figure 226 – Port Selector Overview........................................................................................... 547

Figure 227 – Example Failover Application with Two Hosts ....................................................... 548

Figure 228 – Port selection signal based on assertion of COMRESET to assertion of following

COMRESET ........................................................................................................................ 550

Figure 229 – Complete port selection signal consisting of two sequences with requisite inter-reset

spacings............................................................................................................................... 551

Figure 230 – Control State Machine............................................................................................ 553

Figure 231 – Phy Block Diagram................................................................................................. 554

Figure 232 – Concept summary interconnect structure .............................................................. 584

Figure 233 – An example of signal connections with one I/O Controller..................................... 585

Figure 234 – Example of signal connections with two I/O Modules ............................................ 587

Figure 235 – High Speed Channels – Configuration 0................................................................ 588

Figure 236 – High-Speed Channels – Configuration 1 ............................................................... 588

Figure 237 – Low Speed Channels ............................................................................................. 589

Figure 238 – Interconnect Channels ........................................................................................... 589

Figure 239 – I/O Controller Module Connector Rendering.......................................................... 590

Figure 240 – Connector Pin Layout and Pin Lengths.................................................................. 591

Figure 241 – I/O Controller Module Connector Receptacle Engineering Drawing...................... 592

Figure 242 – Side View of Connector.......................................................................................... 592

Figure 243 – I/O Controller Module Connector Locations on 1xWide I/O module ...................... 594

Figure 244 – I/O Controller Module Connector Locations on 2xWide I/O Module ...................... 595

Serial ATA Revision 2.6 xix

TABLE OF TABLES

Table 1 – State Table Cell Description .......................................................................................... 41

Table 2 – Usage Model Descriptions............................................................................................. 46

Table 3 – Signal and Power SATA Plug and Nominal Mate Sequence ........................................ 76

Table 4 – Allowed values for dimension A and B for device-to-backplane mating ....................... 85

Table 5 – Housing and contact electrical parameters, test procedures, and requirements .......... 89

Table 6 – Mechanical test procedures and requirements ............................................................. 90

Table 7 – Environmental parameters, test procedures, and requirements ................................... 91

Table 8 – Additional requirement................................................................................................... 91

Table 9 – Connector test sequences............................................................................................. 92

Table 10 – Signal and Power Internal Micro SATA Plug and Nominal Mate Sequence ............. 113

Table 11 – Unique Connector Mechanical Testing Procedures and Requirements ................... 114

Table 12 – Slimline Connector Location References .................................................................. 116

Table 13 – Slimline Device plug connector pin definition ............................................................ 121

Table 14 – Slimline Connector Mechanical Test Procedures And Requirements ...................... 128

Table 15 – Multilane Pin Assignments ........................................................................................ 142

Table 16 – Internal Cable / Connector Measurement Parameter and Requirements................. 146

Table 17 – External Single Lane Cable / Connector Measurement Parameter and Requirements

............................................................................................................................................. 146

Table 18 – Limited External Multilane Cable / Connector Measurement Parameter and

Requirements ...................................................................................................................... 147

Table 19 – Extended External Multilane Cable / Connector Measurement Parameter and

Requirements ...................................................................................................................... 147

Table 20 – Common Interconnect Measurement Procedure Methodologies.............................. 150

Table 21 – Interconnect Test Methodologies / Procedures......................................................... 151

Table 22 – Power segment pin P11 activity signal electrical parameters ................................... 157

Table 23 – Host activity signal electrical parameters .................................................................. 157

Table 24 – Activity signal functional states.................................................................................. 158

Table 25 – Host staggered spin-up control electrical requirements ............................................ 159

Table 26 – Comparator voltages for alternate example presence detection circuit .................... 162

Table 27 – General Specifications............................................................................................... 173

Table 28 – Transmitter Specifications ......................................................................................... 174

Table 29 – Transmitted Signal Requirements ............................................................................. 175

Table 30 – Receiver Specifications ............................................................................................. 177

Table 31 – Lab-Sourced Signal (for Receiver Tolerance Testing) .............................................. 178

Table 32 – OOB Specifications ................................................................................................... 180

Table 33 – Low Transition Density Pattern (LTDP) Starting with RD- ........................................ 199

Table 34 – Low Transition Density Pattern (LTDP) starting with RD+ ........................................ 200

Table 35 – High Transition Density Pattern (HTDP) Starting with RD– ...................................... 201

Table 36 – High Transition Density Pattern (HTDP) Starting with RD+ ...................................... 201

Table 37 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD– ..................... 202

Table 38 – Low Frequency Spectral Content Pattern (LFSCP) Starting with RD+..................... 203

Table 39 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD– ....................... 204

Table 40 – Simultaneous Switching Outputs Pattern (SSOP) Starting with RD+ ....................... 204

Table 41 – Lone-Bit Pattern (LBP) Starting with RD– ................................................................. 205

Table 42 – Lone-Bit Pattern (LBP) Starting with RD+ ................................................................. 205

Table 43 – Composite-Bit Pattern (COMP) Starting with RD–.................................................... 206

Table 44 – Composite-Bit Pattern (COMP) Starting with RD+.................................................... 208

Table 45 – Frame Error Rate Confidence Levels Versus Sample Size ...................................... 225

Table 46 – Bit Error Rate Confidence Levels Versus Sample Size ............................................ 226

Table 47 – OOB Signal Times..................................................................................................... 263

Table 48 – Interface Power States .............................................................................................. 273

Table 49 – State Diagram Host Phy Initialization State Machine................................................ 275

Table 50 – State Diagram Device Phy Initialization State Machine ............................................ 279

Table 51 – Bit Designations......................................................................................................... 290

Table 52 – Conversion Examples................................................................................................ 291

Table 53 – 5B/6B Coding ............................................................................................................ 293

Table 54 – 3B/4B Coding ............................................................................................................ 293

Table 55 – Encoding Examples................................................................................................... 294

Table 56 – Valid Data Characters ............................................................................................... 295

Table 57 – Valid Control Characters ........................................................................................... 299

Table 58 – Single Bit Error with Two Character Delay ................................................................ 301

Table 59 – Single Bit Error with One Character Delay ................................................................ 301

Table 60 – Description of Primitives ............................................................................................ 303

Table 61 – Primitive Encoding..................................................................................................... 304

Table 62 – CONT

Usage Example ............................................................................................ 306

Table 63 – Example of Components of a Round Trip Delay....................................................... 309

Table 64 – SRST Write from Host to Device Transmission Breaking Through a Device to Host

Data FIS............................................................................................................................... 310

Table 65 – Command Shadow Register Block Register Transmission Example ....................... 310

Table 66 – Data from Host to Device Transmission Example..................................................... 311

Table 67 – State Diagram Link Idle ............................................................................................. 314

Table 68 – State Diagram Link Transmit..................................................................................... 317

Table 69 – State Diagram Link Receive ...................................................................................... 324

Table 70 – State Diagram Link Power Mode............................................................................... 330

Table 71 – Simplified Shadow Register Block register numbering ............................................. 336

Table 72 – BIST Activate FIS Modes and Bit Settings ................................................................ 347

Table 73 – IDENTIFY DEVICE information ................................................................................. 433

Table 74 – IDENTIFY PACKET DEVICE information ................................................................. 439

Table 75 – SCR definition............................................................................................................ 500

Table 76 – SCR Definition ........................................................................................................... 500

Table 77 – State Diagram Collisions ........................................................................................... 521

Table 78 – State Diagram Hot Plug State Machine for Host Port ............................................... 523

Table 79 – State Diagram Hot Plug State Machine for Device Port............................................ 525

Table 80 – Register Values for an Unsupported Command ....................................................... 528

Table 81 – Static Information Registers ...................................................................................... 530

Table 82 – Status Information and Control Registers ................................................................. 532

Table 83 – Features Supported Registers .................................................................................. 536

Table 84 – Features Enabled Registers ...................................................................................... 537

Table 85 – Vendor Unique Registers .......................................................................................... 538

Table 86 – Phy Event Counter Registers .................................................................................... 539

Table 87 – Reserved Registers ................................................................................................... 539

Table 88 – PSCR Definition......................................................................................................... 540

Table 89 – READ PORT MULTIPLIER Command Definition ..................................................... 540

Table 90 – READ PORT MULTIPLIER Success Status Result Values ...................................... 541

Table 91 – READ PORT MULTIPLIER Error Status Result Values............................................ 542

Table 92 – WRITE PORT MULTIPLIER Command Definition .................................................... 542

Table 93 – WRITE PORT MULTIPLIER Success Status Result Values .................................... 543

Table 94 – WRITE PORT MULTIPLIER Error Status Result Values .......................................... 544

Table 95 – Port selection signal inter-reset timing requirements ................................................ 550

Table 96 – CRC and scrambler calculation example - PIO Write Command ............................. 570

Table 97 – J1, J2, J3 Pin Assignments ....................................................................................... 596

Table 98 – J4, J5, J6 Pin Assignments ....................................................................................... 596

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