ARM架构参考手册：深入解析ARM体系

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"ARM Architecture Reference Manual" 本文档是ARM架构的权威参考指南，涵盖了ARM处理器体系结构的详细信息。ARM体系结构是嵌入式和移动计算领域广泛采用的一种设计，它在微处理器行业中占据了重要的地位。手册由ARM Limited出版，版权覆盖1996年至2005年。 ARMDDI0100I是该文档的特定版本标识，通常ARM会定期更新其技术文档以反映最新的架构改进和技术发展。本手册包含了自1996年以来的多次修订，确保用户能够获取到最新、最准确的信息。 "Release Information"部分提到，文档经历了多次更新，这表明ARM不断对内容进行修正和增强，以反映产品开发和改进的实际情况。同时，文档还包含了一项专有声明，指出ARM、ARMPowered、Thumb、StrongARM等是ARM Limited的注册商标，而其他提及的产品或服务可能是各自所有者的商标。 ARM Architecture Reference Manual的核心内容包括但不限于以下方面： 1. **指令集架构（ISA）**：详细介绍了ARM的指令集，包括数据处理指令、分支指令、浮点运算指令、内存访问指令等。ARM处理器支持多种指令集模式，如 ARM 模式和 Thumb 模式，其中Thumb是一种更紧凑的16位指令集，用于提高代码密度。 2. **处理器核心**：涵盖了各种ARM处理器核心，如ARM7TDMI、ARM9TDMI、ARM9E-S等。每个核心都有其独特的特性和性能指标，适用于不同的应用领域。 3. **系统架构**：描述了如何将ARM处理器集成到更大的系统中，包括内存管理单元（MMU）、中断控制器、总线接口等组件。 4. **开发工具支持**：讨论了ARM开发工具，如ARMulator（模拟器）、Embedded ICE（嵌入式ICE调试工具）、Multi-ICE（多ICE调试器）等，这些都是软件开发者调试和优化ARM应用程序的关键工具。 5. **调试技术**：提供了关于嵌入式调试技术的信息，如ETM（事件追踪模块）和TDMI（调试接口），这些技术对于高效地诊断和修复代码问题至关重要。 6. **知识产权（IP）模块**：介绍了一系列的ARM PrimeCell IP核，这些预设计的模块可以加速SoC（系统级芯片）的开发过程。 7. **软件开发**：指导开发者如何针对ARM架构编写高效的代码，包括编译器选项、优化策略以及与操作系统和库的交互。 8. **许可证条款**：文档末尾的许可证条款规定了用户可以无限制、非排他性、不可转让地在全球范围内使用此ARM架构信息，但同时也明确了这些信息的使用限制。 "ARM Architecture Reference Manual"是学习和理解ARM处理器体系结构的必备资料，无论你是硬件设计师、软件开发者还是系统集成者，都能从中获取到深入且全面的知识，以便在实际项目中充分利用ARM的优势。

Preface

• The restriction that multiplication destination registers should be different from their source registers

is removed in ARMv6.

• In ARMv5, the

LDM

(2) and

STM

(2) ARM instructions have restrictions on the use of banked registers

by the immediately following instruction. These restrictions are removed from ARMv6.

• The rules determining which PSR bits are updated by an

MSR

instruction are clarified and extended to

cover the new PSR bits defined in ARMv6.

• In ARMv5, the Thumb

MOV

instruction behavior varies according to the registers used (see note). Two

changes are made in ARMv6.

— The restriction about the use of low register numbers in the

MOV

(3) instruction encoding is

removed.

— In order to make the new side-effect-free

MOV

instructions available to the assembler language

programmer without changing the meaning of existing assembler sources, a new assembler

syntax

CPY Rd,Rn

is introduced. This always assembles to the

MOV

(3) instruction regardless of

whether Rd and Rn are high or low registers.

Note

In ARMv5, the Thumb

MOV Rd,Rn

instructions have the following properties:

• If both Rd and Rn are low registers, the instruction is the

MOV

(2) instruction. This instruction sets the

N and Z flags according to the value transferred, and sets the C and V flags to 0.

• If either Rd or Rn is a high register, the instruction is the

MOV

(3) instruction. This instruction leaves

the condition flags unchanged.

This situation results in behavior that varies according to the registers used. The

MOV

(2) side-effects also limit

compiler flexibility on use of pseudo-registers in a global register allocator.

Naming of ARM/Thumb architecture versions

To name a precise version and variant of the ARM/Thumb architecture, the following strings are

concatenated:

1. The string

ARMv

2. The version number of the ARM instruction set.

3. Variant letters of the included variants.

4. In addition, the letter P is used after x to denote the exclusion of several instructions in the

ARMv5TExP variant.

The table Architecture versions on page xvii lists the standard names of the current (not obsolete)

ARM/Thumb architecture versions described in this manual. These names provide a shorthand way of

describing the precise instruction set implemented by an ARM processor. However, this manual normally

uses descriptive phrases such as T variants of architecture version 4 and above to avoid the use of lists of

architecture names.

Preface

Part B - Memory and System Architectures

Part B describes standard memory system features that are normally implemented by the System Control

coprocessor (coprocessor 15) in an ARM-based system. It contains the following chapters:

Chapter B1 Gives a brief overview of this part of the manual.

Chapter B2 The memory order model.

Chapter B3 Gives a general description of the System Control coprocessor and its use.

Chapter B4 Describes the standard ARM memory and system architecture based on the use of a Virtual

Memory System Architecture (VMSA) based on a Memory Management Unit (MMU).

Chapter B5 Gives a description of the simpler Protected Memory System Architecture (PMSA) based on

a Memory Protection Unit (MPU).

Chapter B6 Gives a description of the standard ways to control caches and write buffers in ARM

memory systems. This chapter is relevant both to systems based on an MMU and to systems

based on an MPU.

Chapter B7 Describes the Tightly Coupled Memory (TCM) architecture option for level 1 memory.

Chapter B8 Describes the Fast Context Switch Extension and Context ID support (ARMv6 only).

Part C - Vector Floating-point Architecture

Part C describes the Vector Floating-point (VFP) architecture. This is a coprocessor extension to the ARM

architecture designed for high floating-point performance on typical graphics and DSP algorithms.

Chapter C1 Gives a brief overview of the VFP architecture and information about its compliance with

the IEEE 754-1985 floating-point arithmetic standard.

Chapter C2 Describes the floating-point formats supported by the VFP instruction set, the floating-point

general-purpose registers that hold those values, and the VFP system registers.

Chapter C3 Describes the VFP coprocessor instruction set, organized by type of instruction.

Chapter C4 Contains detailed reference material on the VFP coprocessor instruction set, organized

alphabetically by instruction mnemonic.

Chapter C5 Contains detailed reference material on the addressing modes used by VFP instructions.

One of these is a traditional addressing mode, generating addresses for load/store

instructions. The remainder specify how the floating-point general-purpose registers and

instructions can be used to hold and perform calculations on vectors of floating-point values.

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