多异步时钟设计的综合与脚本技术

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"CummingsSNUG2001SJ_AsyncClk" 在现代集成电路（ASIC）设计中，异步时钟设计是常见的挑战。本文档，"CummingsSNUG2001SJ_AsyncClk"，由Clifford E. Cummings撰写，详细探讨了在系统级使用SystemVerilog和Verilog进行异步时钟设计的综合和脚本技术。它特别关注如何处理多异步时钟设计中的数据、控制信号以及验证问题，以确保设计能够按时完成并具备强大的工作能力。 1.0 引言传统的工程教育通常强调单一时钟同步逻辑的设计方法。然而，在实际的ASIC设计领域，几乎不存在完全基于单一时钟的设计。这篇论文的目的在于介绍硬件设计、时序分析、综合和仿真等方法，以应对多时钟设计中的复杂性。 2. 异步时钟设计的核心问题多时钟设计需要处理的关键问题包括时钟域交叉（CDC）、数据同步、亚稳态以及时序收敛。时钟域交叉可能导致数据在不同时钟域间的错误传输，而亚稳态则会影响数据的稳定性和可靠性。因此，设计师需要掌握有效的CDC解决方案，如异步 FIFO、锁相环（PLL）和延迟锁定环（DLL）等。 3. 综合策略在综合阶段，正确地处理异步时钟至关重要。这包括设置适当的约束，如时钟之间的相位关系，以及使用特定的综合工具功能来处理跨时钟边界的信号。时钟门控和时钟使能的使用可以减少亚稳态的风险。 4. 脚本技术为了提高效率和自动化，设计师通常会编写脚本来驱动综合过程。这些脚本可以自动配置约束，执行预综合检查，并在设计流程的不同阶段进行报告和分析。 5. 时序分析与验证确保所有时钟域都满足时序要求是多时钟设计的一个关键步骤。使用专门的时序分析工具，设计师可以检查时钟路径，识别潜在的时序违规，并对设计进行优化。 6. 验证挑战异步设计的验证需要特殊的方法，例如使用形式验证、随机化测试平台和时钟域转换的断言。这些方法帮助确保在不同时钟域间正确传输数据，并避免潜在的问题。 7. 结论虽然多异步时钟设计带来了许多挑战，但通过深入了解硬件设计原理、合成技巧和仿真技术，设计师可以有效地管理这些问题，创建出稳健的多时钟系统。本文提供的信息对于那些希望深入理解异步时钟设计的人来说，是一份宝贵的资源。 "CummingsSNUG2001SJ_AsyncClk"涵盖了从设计概念到实现的全过程，对于任何在异步时钟设计领域工作的工程师来说，都是一个值得参考的学习资料。

SNUG San Jose 2001 Synthesis and Scripting Techniques for

Rev 1.2 Designing Multi-Asynchronous Clock Designs

Timing analysis on modules with two or more asynchronous clocks is error prone, more difficult and can be time

consuming. Static timing analysis on signals generated from one clock domain and latched into sequential elements

within a second, asynchronous clock domain is inaccurate and for the most part worthless. The timing information

for a signal latched by a clock that is asynchronous to the latched signal is inaccurate because the phase relationship

between the signal and the asynchronous clock is always changing; therefore, the static timing analysis tool would

have to check an infinite number of phase relationships between the signal and asynchronous clock. The fact is, one

must assume that signals that pass from one clock domain to another at some point will violate either setup or hold

times on the destination sequential element.

There is no good reason to perform timing analysis on signals that are generated in one clock domain and registered

in another asynchronous clock domain. It is a given that these signals DO violate setup and hold times on the

destination register. This is why synchronizers (see section 3.0) are needed, to alleviate the problems that can occur

when a signal is passed from one clock domain to another.

For RTL modules that have two or more asynchronous clocks as inputs, a designer will be required to indicate to the

static timing analysis tool which signal paths should be ignored. This is accomplished by "setting false paths" on

signals that cross from one clock domain to another. This can be a tedious and error prone job unless the guidelines

in the next two sections are followed.

5.0 Clock Naming Conventions

Guideline: Use a clock naming convention to identify the clock source of every signal in a design.

Reason: A naming convention helps all team members to identify the clock domain for every signal in a design and

also makes grouping of signals for timing analysis easier to do using regular expression "wild-carding" from within

a synthesis script.

A number of useful clock naming conventions have been used by various design teams. One that was used by

design engineers in 1995 while designing video ASICs for In Focus projectors required that a leading prefix

character be used to identify the various asynchronous clock domains. Examples included: uClk for the

microprocessor clock, vClk for the video clock and dClk for the display clock.

Each signal was synchronized to one of the clock domains in the design and each signal-name had to include a

prefix character identifying the clock domain for that signal. Any signal that was clocked by the uClk would have a

u-prefix in the signal name, such as uaddr, udata, uwrite, etc. Any signal that was clocked by the vClk would

similarly have a v-prefix in the signal name, such as vdata, vhsync, vframe, etc. The same signal naming convention

was used for all signals generated by any of the other clocks in the design.

Using this technique, any engineer on the ASIC design team could easily identify the clock-domain source of any

signal in the design and either use the signals directly or pass the signals through a synchronizer so that they could

be used within a new clock domain.

The naming convention alone contributed significantly to the productivity of the design team. How do we know

there was a productivity gain? One of the design engineers started his part of the ASIC design using his own naming

convention, ignoring the convention in use by the other design team members. After much confusion about the

signals entering and leaving his design partition, a team meeting was called and the non-compliant designer was

"strongly encouraged" to rename the signals in his part of the design to conform to the team naming convention.

After the signal names were changed, it became easier to interface to the partition in question. Fewer questions and

less confusions occurred after the change.

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多异步时钟设计的综合与脚本技术

CummingsSNUG2002SJ_FIFO1_rev1_1.pdf

CummingsSNUG2002SJ_FIFO1.pdf

[异步FIFO设计]CummingsSNUG2002SJ_FIFO.rar

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