Freescale MPC8641D 处理器家族参考手册

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"MPC8641D Integrated Host Processor Family Reference Manual" 该文档是Freescale Semiconductor公司关于MPC8641D系列处理器的详细参考手册，版本为Rev.2，发布日期为2008年7月。手册涵盖了MPC8640、MPC8640D、MPC8641以及MPC8641DRM等处理器型号，是了解和使用这些嵌入式处理器的重要资料。 MPC8641D是一款集成主机处理器，基于Power Architecture技术，这是由Power.org授权的商标。该处理器家族旨在提供高性能、低功耗的解决方案，适用于各种嵌入式系统应用。处理器可能包含多个核心，支持多线程处理，具有高效能计算能力，同时在硬件层面支持网络和通信协议，如IEEE 802.3（以太网）、IEEE 802.1（局域网管理）等。文档中的内容可能包括以下部分： 1. **处理器架构**：详细描述了MPC8641D的微架构，包括CPU核心、缓存结构、内存接口以及I/O接口。 2. **指令集**：涵盖了处理器支持的指令集，可能是PowerPC的增强型64位ISA，包括数据处理、控制流、负载和存储指令等。 3. **性能特性**：包括处理器的时钟速度、功耗、电压范围以及热设计功率(TDP)等。 4. **接口和外设**：详细说明了与处理器连接的各种接口，如PCI、PCI-X、PCI Express，以及串行ATA、USB、以太网MAC等外设控制器。 5. **系统管理**：涵盖电源管理、温度监控、错误检测与校正（ECC）机制，以及符合IEEE 1149.1标准的边界扫描测试（JTAG）接口。 6. **开发工具和支持**：可能提到了开发板、调试工具、软件开发套件（SDK）以及编译器等资源。 7. **硬件设计指南**：指导如何在系统级设计中集成MPC8641D处理器，包括PCB布局建议和电气规范。 8. **软件接口**：描述了操作系统支持、固件加载、中断处理和设备驱动程序的编程接口。 9. **安全特性**：可能包括加密硬件加速器、安全启动机制和信任根(Root of Trust)功能。 10. **故障排除和诊断**：提供了故障排除策略和诊断工具的信息。请注意，虽然文档包含了丰富的技术信息，但不授予任何关于设计或制造基于文档信息的集成电路的版权许可。Freescale Semiconductor保留随时更改产品而不另行通知的权利。所有其他产品和服务名称属于各自所有者的财产。

MPC8641D Integrated Host Processor Family Reference Manual, Rev. 2

xvi Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

9.1 Introduction...................................................................................................................... 9-1

9.1.1 Overview...................................................................................................................... 9-1

9.1.2 The PIC in Multiple-Processor Implementations ........................................................ 9-4

9.1.3 Interrupts to the Processor Core................................................................................... 9-4

9.1.4 Modes of Operation ..................................................................................................... 9-5

9.1.4.1 Mixed Mode (GCR[M] = 1) .................................................................................... 9-5

9.1.4.2 Pass-Through Mode (GCR[M] = 0) ........................................................................ 9-5

9.1.5 Interrupt Sources..........................................................................................................9-6

9.1.5.1 Interrupt Routing—Mixed Mode............................................................................. 9-6

9.1.5.2 Interrupt Destinations .............................................................................................. 9-7

9.1.5.3 Internal Interrupt Sources ........................................................................................ 9-7

9.2 External Signal Descriptions ........................................................................................... 9-8

9.2.1 Signal Overview .......................................................................................................... 9-8

9.2.2 Detailed Signal Descriptions ....................................................................................... 9-9

9.3 Memory Map/Register Definition ................................................................................... 9-9

9.3.1 Global Registers......................................................................................................... 9-18

9.3.1.1 Block Revision Register 1 (BRR1)........................................................................ 9-18

9.3.1.2 Block Revision Register 2 (BRR2)........................................................................ 9-19

9.3.1.3 Feature Reporting Register (FRR)......................................................................... 9-19

9.3.1.4 Global Configuration Register (GCR)................................................................... 9-20

9.3.1.5 Vendor Identification Register (VIR) .................................................................... 9-21

9.3.1.6 Processor Core Initialization Register (PIR) .........................................................9-21

9.3.1.7 Processor Reset Register (PRR) ............................................................................ 9-22

9.3.1.8 Interprocessor Interrupt Vector/Priority Registers (IPIVPR0–IPIVPR3).............. 9-23

9.3.1.9 Spurious Vector Register (SVR)............................................................................ 9-23

9.3.2 Global Timer Registers.............................................................................................. 9-24

9.3.2.1 Timer Frequency Reporting Register (TFRRA–TFRRB) ..................................... 9-24

9.3.2.2 Global Timer Current Count Registers (GTCCRA0–GTCCRA3,

GTCCRB0–GTCCRB3)..................................................................................... 9-25

9.3.2.3 Global Timer Base Count Registers (GTBCRA0–GTBCRA3,

GTBCRB0–GTBCRB3)..................................................................................... 9-25

9.3.2.4 Global Timer Vector/Priority Registers (GTVPRA0–GTVPRA3,

GTVPRB0–GTVPRB3)..................................................................................... 9-26

9.3.2.5 Global Timer Destination Registers (GTDRA0–GTDRA3,

GTDRB0–GTDRB3).......................................................................................... 9-27

9.3.2.6 Timer Control Registers (TCRA–TCRB).............................................................. 9-27

9.3.3 IRQ_OUT and Critical Interrupt Summary Registers ............................................... 9-29

9.3.3.1 External Interrupt Summary Register (ERQSR) ................................................... 9-29

9.3.3.2 IRQ_OUT Summary Register 0 (IRQSR0)........................................................... 9-30

9.3.3.3 IRQ_OUT Summary Register 1 (IRQSR1)........................................................... 9-31

9.3.3.4 IRQ_OUT Summary Register 2 (IRQSR2)........................................................... 9-31

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Contents

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Number Title

Page

Number

9.3.3.5 Critical Interrupt Summary Register 0 (CISR0).................................................... 9-32

9.3.3.6 Critical Interrupt Summary Register 1 (CISR1).................................................... 9-32

9.3.3.7 Critical Interrupt Summary Register 2 (CISR2).................................................... 9-33

9.3.4 Performance Monitor Mask Registers (PMMRs)...................................................... 9-33

9.3.4.1 Performance Monitor Mask Registers 0 (PM0MR0–PM3MR0) .......................... 9-33

9.3.4.2 Performance Monitor Mask Registers 1 (PM0MR1–PM3MR1) .......................... 9-34

9.3.4.3 Performance Monitor Mask Registers 2 (PM0MR2–PM3MR2) .......................... 9-35

9.3.5 Message Registers...................................................................................................... 9-35

9.3.5.1 Message Registers (MSGR0–MSGR3) ................................................................. 9-35

9.3.5.2 Message Enable Register (MER)........................................................................... 9-36

9.3.5.3 Message Status Register (MSR) ............................................................................ 9-36

9.3.6 Shared Message Signaled Registers .......................................................................... 9-37

9.3.6.1 Shared Message Signaled Interrupt Registers (MSIR0–MSIR7).......................... 9-37

9.3.6.2 Shared Message Signaled Interrupt Status Register (MSISR)............................... 9-38

9.3.6.3 Shared Message Signaled Interrupt Index Register (MSIIR)................................ 9-38

9.3.6.4 Shared Message Signaled Interrupt Vector/Priority Register (MSIVPRs)............ 9-39

9.3.6.5 Shared Message Signaled Interrupt Destination Registers 0–7 (MSIDRn)........... 9-40

9.3.7 Interrupt Source Configuration Registers.................................................................. 9-40

9.3.7.1 External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ....................... 9-42

9.3.7.2 External Interrupt Destination Registers (EIDR0–EIDR11) .................................9-43

9.3.7.3 Internal Interrupt Vector/Priority Registers (IIVPRn)...........................................9-44

9.3.7.4 Internal Interrupt Destination Registers (IIDRn)................................................... 9-45

9.3.7.5 Messaging Interrupt Vector/Priority Registers (MIVPRn).................................... 9-46

9.3.7.6 Messaging Interrupt Destination Registers (MIDR0–MIDR3)............................. 9-46

9.3.8 Per-CPU (Private Access) Registers.......................................................................... 9-47

9.3.8.1 Interprocessor Interrupt Dispatch Register (IPIDR0–IPIDR3) ............................. 9-49

9.3.8.2 Processor Core Current Task Priority Registers 0–1 (CTPR0–CTPR1) ............... 9-49

9.3.8.3 Who Am I Registers 0–1 (WHOAMI0–WHOAMI1)........................................... 9-50

9.3.8.4 Processor Core Interrupt Acknowledge Registers 0–1 (IACK0–IACK1)............. 9-51

9.3.8.5 Processor Core End of Interrupt Registers (EOI0–EOI1) ..................................... 9-51

9.4 Functional Description................................................................................................... 9-52

9.4.1 Flow of Interrupt Control........................................................................................... 9-52

9.4.1.1 Interrupts Routed to cint

or IRQ_OUT.................................................................. 9-52

9.4.1.2 Interrupts Routed to int.......................................................................................... 9-53

9.4.1.2.1 Nesting of Interrupts.......................................................................................... 9-55

9.4.1.2.2 Interrupt Source Priority.................................................................................... 9-55

9.4.1.2.3 Interrupt Acknowledge...................................................................................... 9-56

9.4.1.2.4 Spurious Vector Generation............................................................................... 9-56

9.4.2 Interprocessor Interrupts............................................................................................ 9-56

9.4.3 Message Interrupts..................................................................................................... 9-57

9.4.4 Shared Message Signaled Interrupts.......................................................................... 9-57

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Contents

Paragraph

Number Title

Page

Number

9.4.5 PCI Express INTx...................................................................................................... 9-57

9.4.6 Global Timers ............................................................................................................ 9-58

9.4.7 Resets......................................................................................................................... 9-58

9.4.8 Resetting the PIC ....................................................................................................... 9-59

9.4.8.1 Processor Core Resetting....................................................................................... 9-59

9.4.8.2 Processor Core Initialization.................................................................................. 9-59

9.5 Initialization/Application Information........................................................................... 9-59

9.5.1 Programming Guidelines ........................................................................................... 9-59

9.5.1.1 PIC Registers ......................................................................................................... 9-59

9.5.1.2 Changing Interrupt Source Configuration ............................................................. 9-61

Chapter 10

C Interfaces

10.1 Introduction.................................................................................................................... 10-1

10.1.1 Overview.................................................................................................................... 10-2

10.1.2 Features......................................................................................................................10-2

10.1.3 Modes of Operation ................................................................................................... 10-2

10.2 External Signal Descriptions ......................................................................................... 10-3

10.2.1 Signal Overview ........................................................................................................ 10-3

10.2.2 Detailed Signal Descriptions ..................................................................................... 10-3

10.3 Memory Map/Register Definition ................................................................................. 10-4

10.3.1 Register Descriptions................................................................................................. 10-5

10.3.1.1 I

C Address Register (I2CADR) ........................................................................... 10-5

10.3.1.2 I

C Frequency Divider Register (I2CFDR)...........................................................10-6

10.3.1.3 I

C Control Register (I2CCR) ............................................................................... 10-7

10.3.1.4 I

C Status Register (I2CSR).................................................................................. 10-9

10.3.1.5 I

C Data Register (I2CDR).................................................................................. 10-10

10.3.1.6 Digital Filter Sampling Rate Register (I2CDFSRR) ........................................... 10-11

10.4 Functional Description................................................................................................. 10-11

10.4.1 Transaction Protocol ................................................................................................ 10-11

10.4.1.1 START Condition................................................................................................ 10-12

10.4.1.2 Slave Address Transmission................................................................................ 10-12

10.4.1.3 Repeated START Condition ................................................................................ 10-13

10.4.1.4 STOP Condition................................................................................................... 10-13

10.4.1.5 Protocol Implementation Details ......................................................................... 10-13

10.4.1.5.1 Transaction Monitoring—Implementation Details.......................................... 10-14

10.4.1.5.2 Control Transfer—Implementation Details.....................................................10-14

10.4.1.6 Address Compare—Implementation Details....................................................... 10-15

10.4.2 Arbitration Procedure .............................................................................................. 10-15

10.4.2.1 Arbitration Control .............................................................................................. 10-15

MPC8641D Integrated Host Processor Family Reference Manual, Rev. 2

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Contents

Paragraph

Number Title

Page

Number

10.4.3 Handshaking ............................................................................................................ 10-16

10.4.4 Clock Control........................................................................................................... 10-16

10.4.4.1 Clock Synchronization......................................................................................... 10-16

10.4.4.2 Input Synchronization and Digital Filter ............................................................. 10-16

10.4.4.2.1 Input Signal Synchronization .......................................................................... 10-16

10.4.4.2.2 Filtering of SCL and SDA Lines ..................................................................... 10-17

10.4.4.3 Clock Stretching .................................................................................................. 10-17

10.4.5 Boot Sequencer Mode.............................................................................................. 10-17

10.4.5.1 EEPROM Calling Address .................................................................................. 10-18

10.4.5.2 EEPROM Data Format........................................................................................ 10-19

10.5 Initialization/Application Information......................................................................... 10-21

10.5.1 Initialization Sequence............................................................................................. 10-21

10.5.2 Generation of START .............................................................................................. 10-21

10.5.3 Post-Transfer Software Response............................................................................ 10-22

10.5.4 Generation of STOP................................................................................................. 10-22

10.5.5 Generation of Repeated START .............................................................................. 10-23

10.5.6 Generation of SCL When SDA Low ....................................................................... 10-23

10.5.7 Slave Mode Interrupt Service Routine..................................................................... 10-23

10.5.7.1 Slave Transmitter and Received Acknowledge...................................................10-23

10.5.7.2 Loss of Arbitration and Forcing of Slave Mode.................................................. 10-24

10.5.8 Interrupt Service Routine Flowchart........................................................................ 10-24

Chapter 11

DUART

11.1 Overview........................................................................................................................ 11-1

11.1.1 Features...................................................................................................................... 11-1

11.1.2 Modes of Operation ................................................................................................... 11-2

11.1.2.1 DUART Signal Mode Selection ............................................................................ 11-3

11.2 External Signal Descriptions ......................................................................................... 11-3

11.2.1 Signal Overview ........................................................................................................ 11-3

11.2.2 Detailed Signal Descriptions ..................................................................................... 11-3

11.3 Memory Map/Register Definition ................................................................................. 11-4

11.3.1 Register Descriptions................................................................................................. 11-5

11.3.1.1 Receiver Buffer Registers (URBRn) (ULCR[DLAB] = 0) ................................... 11-5

11.3.1.2 Transmitter Holding Registers (UTHRn) (ULCR[DLAB] = 0) ............................ 11-5

11.3.1.3 Divisor Most and Least Significant Byte Registers (UDMB and UDLB)

(ULCR[DLAB] = 1) .......................................................................................... 11-6

11.3.1.4 Interrupt Enable Register (UIER) (ULCR[DLAB] = 0)........................................ 11-8

11.3.1.5 Interrupt ID Registers (UIIRn) (ULCR[DLAB] = 0) ............................................ 11-8

11.3.1.6 FIFO Control Registers (UFCRn) (ULCR[DLAB] = 0) ..................................... 11-10

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Contents

Paragraph

Number Title

Page

Number

11.3.1.7 Line Control Registers (ULCRn)..........................................................................11-11

11.3.1.8 Modem Control Registers (UMCRn) .................................................................. 11-13

11.3.1.9 Line Status Registers (ULSRn) ........................................................................... 11-14

11.3.1.10 Modem Status Registers (UMSRn) ..................................................................... 11-15

11.3.1.11 Scratch Registers (USCRn) ................................................................................. 11-16

11.3.1.12 Alternate Function Registers (UAFRn) (ULCR[DLAB] = 1)............................. 11-16

11.3.1.13 DMA Status Registers (UDSRn) ......................................................................... 11-17

11.4 Functional Description................................................................................................. 11-18

11.4.1 Serial Interface......................................................................................................... 11-19

11.4.1.1 START Bit ........................................................................................................... 11-19

11.4.1.2 Data Transfer ....................................................................................................... 11-20

11.4.1.3 Parity Bit.............................................................................................................. 11-20

11.4.1.4 STOP Bit.............................................................................................................. 11-20

11.4.2 Baud-Rate Generator Logic..................................................................................... 11-20

11.4.3 Local Loopback Mode............................................................................................. 11-21

11.4.4 Errors ....................................................................................................................... 11-21

11.4.4.1 Framing Error ...................................................................................................... 11-21

11.4.4.2 Parity Error .......................................................................................................... 11-21

11.4.4.3 Overrun Error....................................................................................................... 11-21

11.4.5 FIFO Mode .............................................................................................................. 11-21

11.4.5.1 FIFO Interrupts.................................................................................................... 11-22

11.4.5.2 DMA Mode Select............................................................................................... 11-22

11.4.5.3 Interrupt Control Logic........................................................................................ 11-22

11.5 DUART Initialization/Application Information .......................................................... 11-23

Chapter 12

Local Bus Controller

12.1 Introduction.................................................................................................................... 12-1

12.1.1 Overview.................................................................................................................... 12-2

12.1.2 Features......................................................................................................................12-2

12.1.3 Modes of Operation ................................................................................................... 12-3

12.1.3.1 LBC Bus Clock and Clock Ratios ......................................................................... 12-3

12.1.3.2 Source ID Debug Mode......................................................................................... 12-4

12.1.4 Power-Down Mode.................................................................................................... 12-4

12.2 External Signal Descriptions ......................................................................................... 12-4

12.3 Memory Map/Register Definition ................................................................................. 12-8

12.3.1 Register Descriptions............................................................................................... 12-10

12.3.1.1 Base Registers (BR0–BR7) ................................................................................. 12-10

12.3.1.2 Option Registers (OR0–OR7).............................................................................. 12-12

12.3.1.2.1 Address Mask .................................................................................................. 12-12

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