DS90UH949A-Q1：汽车级HDMI到FPD-LinkIII串行器

需积分: 10 129 浏览量更新于2024-06-27 4 收藏 2.13MB PDF 举报

"TI-DS90UH949A-Q1.pdf 是关于TI公司的一款汽车级FPD-Link串行器芯片DS90UH949A-Q1的详细资料，该芯片用于实现HDMI到FPD-LinkIII的桥接转换。" TI的DS90UH949A-Q1是一款高性能的串行器，设计用于汽车应用，符合AEC-Q100标准，确保了在恶劣环境条件下的可靠性。它具备第二温度等级的耐温能力，可以在-40°C至105°C的范围内稳定工作，并具有第二等级的HBM ESD保护和C5等级的CDM ESD保护，增强了设备的抗静电干扰性能。该芯片支持高达210MHz的TMDS时钟频率，这意味着它可以处理2K分辨率（2880x1080）的视频信号，同时支持24位色彩深度，确保了高质量的视频传输。DS90UH949A-Q1提供单通道和双通道FPD-LinkIII输出，可以适应不同的系统需求，支持使用屏蔽双绞线(STP)或屏蔽四绞线(STQ)电缆进行长距离传输。此串行器集成了HDMI输入接口，包括DDC、CEC功能，能够与HDMI源设备无缝对接。HDMI的DDC（Display Data Channel）允许串行传输显示配置信息，而CEC（Consumer Electronics Control）则允许设备间的控制信号通信。此外，DS90UH949A-Q1还支持HDCP（High-Bandwidth Content Protection），确保了内容的版权保护。芯片内部还包括GPIO（General-Purpose Input/Output）引脚，可以通过SPI（Serial Peripheral Interface）进行配置，为用户提供了额外的控制和扩展功能。同时，DS90UH949A-Q1可以与解串器DS90UH948-Q1配合使用，形成完整的串行链路，连接LVDSDisplay或图形处理器。该设备还支持I2C通信，可以方便地与其他系统组件进行交互。工作电压包括3.3V和1.8V，满足不同电源需求。其HDMI输入端口支持Hot Plug Detect (HPD)功能，能够检测到设备的连接和断开。 DS90UH949A-Q1是汽车电子领域中一款强大的视频接口解决方案，它将高清多媒体接口（HDMI）与FPD-LinkIII串行技术结合，提供了高效、安全的视频信号传输途径，尤其适用于需要高质量视频显示的车载娱乐和信息系统。在实际设计应用前，设计者应参考最新的英文数据表以获取最准确的技术信息。

FPD-Link III Digital

HDMI Controller

Digital

HDMI RX

PHY

FPD-Link

III TX

Digital

FPD3 TX

Analog

Bridge Control

Digital

TMDS

DDC

HPA

FPD-Link III

Audio

PLL

Audio

FIFO

Packet

FIFO

KSV

FIFO

EDID/

Config

NVM

EDID

I/F

I2S Audio

Video

HDCP

Key

NVM

RX_5V

I2C

Optional

Secondary

I2S

Digital

TMDS

Interface

FPD3 TX

Analog

FPD-Link III

FPD-Link

III TX

Digital

PAT

GEN

DS90UH949A-Q1

www.ti.com.cn

ZHCSIO8 –AUGUST 2018

7 Detailed Description

7.1 Overview

The DS90UH949A-Q1 converts an HDMI interface (3 TMDS data channels + 1 TMDS Clock) to an FPD-Link III

interface. This device transmits a 35-bit symbol operating at up to 3.675-Gbps line rate over either a single serial

pair or two serial pairs. The serial stream contains an embedded clock, video control signals, RGB video data,

and audio data. The payload is DC-balanced to enhance signal quality and support AC coupling.

The DS90UH949A-Q1 serializer is intended for use with a DS90UH926Q-Q1, DS90UH928Q-Q1, DS90UH940A-

Q1, and DS90UH948A-Q1 deserializer.

The DS90UH949A-Q1 serializer and companion deserializer can incorporate an I

C-compatible interface. The

C-compatible interface supports the programming of serializer or deserializer devices from a local host

controller. The devices can also incorporate a bidirectional control channel (BCC) that allows communication

between the serializer and deserializer as well as between remote I2C slave devices.

The bidirectional control channel (BCC) is implemented through embedded signaling in the high-speed forward

channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to

serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial

link from one I2C bus to another. The implementation allows for arbitration with other I2C-compatible masters at

either side of the serial link.

7.2 Functional Block Diagram

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

7.3 Feature Description

7.3.1 High-Definition Multimedia Interface (HDMI)

HDMI is a leading interface standard used to transmit digital video and audio from sources (such as a DVD

player) to sinks (such as an LCD display). The interface is capable of transmitting high-definition video, audio,

and also supports HDCP. Other HDMI signals consist of various control and status data that travel bidirectionally.

7.3.1.1 HDMI Receive Controller

The HDMI Receiver is an HDMI version 1.4b compliant receiver. The HDMI receiver is capable of operation at

greater than 2K resolutions. The configuration used in the DS90UH949A-Q1 does not include version 1.4b

features such as the ethernet channel (HEC) or Audio Return Channel (ARC).

7.3.2 Transition Minimized Differential Signaling

HDMI uses Transition Minimized Differential Signaling (TMDS) over four differential pairs (3 TMDS channels and

1 TMDS clock) to transmit video and audio data. TMDS is widely used to transmit high-speed serial data. The

technology incorporates a form of 8b/10b encoding, and the differential signaling allows the device to reduce

electromagnetic interference (EMI) and achieve high skew tolerance.

7.3.3 Enhanced Display Data Channel

The Display Data Channel (DDC) is a collection of digital communication protocols between a computer display

and a graphics adapter that enables the display to send the supported display modes to the adapter. The DDC

also allows the computer host to adjust monitor parameters, such as brightness and contrast.

7.3.4 Extended Display Identification Data (EDID)

EDID is a data structure provided by a digital display to describe the display capabilities to a video source. By

providing this information, the video source can then send video data with the proper timing and resolution that

the display supports. The DS90UH949A-Q1 supports several options for delivering display identification (EDID)

information to the HDMI graphics source. The EDID information is accessible through the DDC interface and

comply with the DDC and EDID requirements given in the HDMI v1.4b specification.

The EDID configurations supported are as follows:

• External local EDID (EEPROM)

• Internal EDID loaded into device memory

• Remote EDID connected to I2C bus at deserializer side

• Internal pre-programmed EDID

The EDID mode selected should be configurable from the MODE_SEL pins or from internal control registers. For

all modes, the EDID information should be accessible at the default address of 0xA0.

7.3.4.1 External Local EDID (EEPROM)

The DS90UH949A-Q1 can be configured to allow a local EEPROM EDID device. The local EDID device may

implement any EDID configuration allowable by the HDMI v1.4b and DVI 1.0 standards, including multiple

extension blocks up to 32KB.

7.3.4.2 Internal EDID (SRAM)

The DS90UH949A-Q1 also allows the internal loading of an EDID profile up to 256 bytes. This SRAM storage is

volatile and requires loading from an external I2C master (local or remote). The internal EDID is reloadable and

readable (local/remote) from control registers during normal operation.

7.3.4.3 External Remote EDID

The serializer copies the remote EDID connected to the I2C bus of the remote deserializer into its internal

SRAM. The remote EDID device can be a standalone I2C EEPROM, or integrated into the digital display panel.

In this mode, the serializer automatically accesses the Bidirectional Control Channel to search for the EDID

information at the default address 0xA0. Once found, the serializer copies the remote EDID into local SRAM.

DS90UH949A-Q1

www.ti.com.cn

ZHCSIO8 –AUGUST 2018

Feature Description (接接下下页页)

7.3.4.4 Internal Pre-Programmed EDID

The serializer also has an internal eFuse that is loaded into the internal SRAM with pre-programmed 256-byte

EDID data at start-up. This EDID profile supports several generic video (480p, 720p) and audio (2-channel audio)

timing profiles within the single-link operating range of the device (25-MHz to 105-MHz pixel clock). In this mode,

the internal EDID SRAM data is readable from the DDC interface. The EDID contents are below:

0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x53 0x0E 0x49 0x09 0x01 0x00 0x00 0x00

0x1C 0x18 0x01 0x03 0x80 0x34 0x20 0x78 0x0A 0xEC 0x18 0xA3 0x54 0x46 0x98 0x25

0x0F 0x48 0x4C 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x01

0x01 0x01 0x01 0x01 0x01 0x01 0x01 0x1D 0x00 0x72 0x51 0xD0 0x1E 0x20 0x6E 0x50

0x55 0x00 0x00 0x20 0x21 0x00 0x00 0x18 0x00 0x00 0x00 0xFD 0x00 0x3B 0x3D 0x62

0x64 0x08 0x00 0x0A 0x20 0x20 0x20 0x20 0x20 0x20 0x00 0x00 0x00 0xFC 0x00 0x54

0x49 0x2D 0x44 0x53 0x39 0x30 0x55 0x78 0x39 0x34 0x39 0x0A 0x00 0x00 0x00 0x10

0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x57

0x02 0x03 0x15 0x40 0x41 0x84 0x23 0x09 0x7F 0x05 0x83 0x01 0x00 0x00 0x66 0x03

0x0C 0x00 0x10 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00

0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x28

7.3.5 Consumer Electronics Control (CEC)

Consumer Electronics Control (CEC) is designed to allow the system user to command and control up to ten

CEC-enabled devices connected through HDMI using only one of their remote controls (for example, controlling

a television set, set-top box, and DVD player using only the remote control of the TV). CEC also allows for

individual CEC-enabled devices to command and control each other without user intervention. CEC is a one-

wire, open-drain bus with an external 27-kΩ (±10%) resistor pullup to 3.3 V.

CEC protocol can be implemented using an external clock reference or the 25-MHz internal oscillator inside the

DS90UH949A-Q1.

7.3.6 +5-V Power Signal

5 V is asserted by the HDMI source through the HDMI interface. The 5-V signal propagates through the

connector and cable until it reaches the sink. The 5-V supply is used for various HDMI functions, such as HPD

and DDC signals.

7.3.7 Hot Plug Detect (HPD)

The HPD pin is asserted by the sink to let the source know that it is ready to receive the HDMI signal. The

source initiates the connection by first providing the 5-V power signal through the HDMI interface. The sink holds

HPD low until it is ready to receive signals from the source, at which point it will release HPD to be pulled up to 5

7.3.8 High-Speed Forward Channel Data Transfer

The High-Speed Forward Channel is composed of 35 bits of data containing RGB data, sync signals, HDCP,

I2C, GPIOs, and I2S audio transmitted from serializer to deserializer. 图 10 shows the serial stream per clock

cycle. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,

balanced, and scrambled.

图图 10. FPD-Link III Serial Stream

DS90UH949A-Q1

ZHCSIO8 –AUGUST 2018

www.ti.com.cn

Feature Description (接接下下页页)

The device supports TMDS clocks in the range of 25 MHz to 105 MHz over one lane, or 50 MHz to 210 MHz

over two lanes. The FPD-Link III serial stream rate is 3.675 Gbps maximum (875 Mbps minimum) when

transmitting either over one lane or both lanes.

7.3.9 Back Channel Data Transfer

The Backward Channel provides bidirectional communication between the display and host processor. The

information is carried from the deserializer to the serializer as serial frames. The back channel control data is

transferred over both serial links along with the high-speed forward data, DC balance coding, and embedded

clock information. This architecture provides a backward path across the serial link together with a high-speed

forward channel. The back channel contains the I2C, HDCP, CRC, and 4 bits of standard GPIO information with

a line rate of 5, 10, or 20 Mbps (configured by the compatible deserializer).

7.3.10 FPD-Link III Port Register Access

The DS90UH949A-Q1 contains two downstream ports, therefore some registers must be duplicated to allow

control and monitoring of the two ports. To facilitate this, a TX_PORT_SEL register controls access to the two

sets of registers. Registers that are shared between ports (not duplicated) will be available independent of the

settings in the TX_PORT_SEL register.

Setting the TX_PORT0_SEL or TX_PORT1_SEL bit will allow a read of the register for the selected port. If both

bits are set, port1 registers will be returned. Writes will occur to ports for which the select bit is set, allowing

simultaneous writes to both ports if both select bits are set.

Setting the PORT1_I2C_EN bit will enable a second I2C slave address, allowing access to the second port

registers through the second I2C address. If this bit is set, the TX_PORT0_SEL and TX_PORT1_SEL bits will be

ignored.

7.3.11 Power Down (PDB)

The Serializer has a PDB input pin to ENABLE or POWER DOWN the device. This pin may be controlled by an

external device, or through V

DDIO

, where V

DDIO

= 1.71 V to 1.89 V. To save power, disable the link when the

display is not required (PDB = LOW). Ensure that this pin is not driven HIGH before all power supplies have

reached final levels. When PDB is driven low, ensure that the pin is driven to 0 V for at least 3 ms before

releasing or driving high. In the case where PDB is pulled up to V

DDIO

directly, a 10-kΩ pullup resistor and a >10-

µF capacitor to ground are required (see ).

Toggling PDB low will POWER DOWN the device and RESET all control registers to default. During this time,

PDB must be held low for a minimum of 3 ms before going high again.

7.3.12 Serial Link Fault Detect

The DS90UH949A-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the

Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x0C (Table 10). The DS90UH949A-Q1 will

detect any of the following conditions:

1. Cable open

2. “+” to “-” short

3. ”+” to GND short

4. ”–” to GND short

5. ”+” to battery short

6. ”–” to battery short

7. Cable is linked incorrectly (DOUT+/DOUT– connections reversed)

注注

The device will detect any of the above conditions, but does not report specifically which

one has occurred.

剩余87页未读，继续阅读

不觉明了

粉丝: 4023
资源: 5759

DS90UH949A-Q1：汽车级HDMI到FPD-LinkIII串行器

TI-DS90UH949-Q1.pdf

TI-DS90UB949A-Q1.pdf

TI-DS90UB949-Q1.pdf

TI-DS90UH947N-Q1.pdf

TI-DS90UH925AQ-Q1.pdf

TI-DS90UH941AS-Q1.pdf

TI-DS90UH928Q-Q1.pdf

TI-DS90UH927Q-Q1.pdf

TI-DS90UH926Q-Q1.pdf

TI-DS90UH925Q-Q1.pdf

最新资源