2014 FPGA开发最佳实践：提升设计质量与效率

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本文档《Best-FPGA-Development-Practices-2014-02-20》由Charles Fulks撰写，发表于Intuitive Research and Technology Corporation，旨在提供一套实用且高效的FPGA开发最佳实践。作者在文中探讨了如何通过改进FPGA设计流程，减少设计错误，从而降低成本并提高系统集成阶段的效率。文章特别关注了PCB设计（Printed Circuit Board Design）和RTL（Register Transfer Level）设计等关键环节，以协助开发者评估不同FPGA开发方案。该论文首先介绍了论文的背景和目标，强调了在FPGA设计过程中避免常见错误的重要性。作者提出了一套设计准则和开发流程，包括但不限于以下几点： 1. **明确的设计过程**：文章提倡采用一种系统化的方法论，从项目规划开始，经过需求分析、设计策略选择、详细设计、仿真验证直至硬件实现，确保每个步骤都得到充分的关注。 2. **PCB设计优化**：FPGA的性能和可靠性很大程度上取决于PCB布局。良好的PCB设计能有效降低信号完整性问题，减少噪声干扰，并确保组件间的高效通信。 3. **RTL设计的最佳实践**：强调了模块化设计、良好的数据流管理、时序分析和同步/异步设计决策的重要性。此外，还推荐使用高级综合工具和技术，如硬件描述语言（HDL），如Verilog或VHDL，以提高代码质量和可维护性。 4. **有效的设计审查**：论文中提到了定期进行同行评审和单元测试的重要性，以发现潜在的设计缺陷，并及时修正。 5. **早期硬件验证**：通过采用模型验证、静态时序分析和动态仿真等方法，确保设计在早期阶段就能发现问题，降低后期调试的成本。 6. **风险管理与文档管理**：文中还提及了对设计风险的识别与管理，以及文档标准化和版本控制，以保持项目的清晰性和一致性。 7. **比较和选择合适的FPGA**：作者建议在评估FPGA时，不仅考虑器件性能，还要考虑开发平台、工具链的支持程度和社区资源等因素。 8. **持续学习和改进**：鼓励开发者不断更新技术知识，跟随业界最新进展，以适应快速发展的FPGA技术。通过遵循这些最佳实践，FPGA设计团队可以显著提高产品质量，缩短开发周期，从而在激烈的市场竞争中取得优势。本文作为设计West Conference 2012上的演讲稿，为FPGA开发者提供了一个实用的参考框架，对于任何从事或计划进入FPGA领域的工程师来说，具有很高的参考价值。

Intuitive Research and Technology Corporation

Best FPGA Development Practices

In Advisory Circular 20-152, the Federal Aviation Administration (FAA) recommends DO-254. RTCA/DO-

254

Design Assurance Guidance For Airborne Electronic Hardware

denes simple electronics and states

that if it is not simple, it is complex.

A hardware item is identied as simple only if a comprehensive combination of deterministic

tests and analyses appropriate to the design assurance level can ensure correct functional

performance under all foreseeable operating conditions with no anomalous behavior.

When

an item cannot be classied as simple, it should be classied as complex

[emphasis

added].

The NASA Assurance Process for Complex Electronics addresses FPGAs as follows.

Complex electronics are programmable devices that can be used to implement specic hard-

ware circuits. The devices that are included under the label of complex electronics are:

•

Complex programmable logic device (CPLD)

•

Field Programmable Gate Array (FPGA)

•

Application Specic Integrated Circuit (ASIC)

•

System on a Chip (SOC)

•

Field Programmable System Chip (FPSC)

•

Variations of FPGAs and ASICs

In the term complex electronics, the complex adjective is used to distinguish between simple

devices, such as o-the-shelf ICs and logic gates, and user-creatable devices.

Note that rmware (which is essentially software stored on a read-only device) is not consid-

ered complex electronics. The integrated circuit (e.g. EEPROM) is simple electronics. The

program stored in that device is software, which has a dened assurance process in place.

1.3 A Minimal Process

Most, if not all, of the process description standards allow for dierent levels of process depending on the

safety criticality of the system. This section describes minimum process for FPGA development for non-safety

critical industries shown in Figure 1.1.

Prioritized Feature List.

We can be reasonably sure that a project's requirements will change at some

point in the program. A Prioritized Feature List attempts two things: it avoids requirements changes

due to misunderstanding of what to build, and it can help us determine what to work on rst. In other

words, what would we want done as soon as possible for a customer demo.

Digital Design.

The digital design must be well dened prior to attempting to capture it in Hardware

Description Language (HDL). The level of documented detail is debatable; however, if you cannot describe

your design with timing diagrams, block diagrams, and text, how can you expect to describe it accurately

with HDL? Documenting a design is key to ensuring that someone else, including a future version of you

can quickly gain an understanding of the design.

Any design not accompanied by documentation is not

acceptable.

Design Capture and Test Bench Capture.

If possible, dierent engineers should capture the design

and the test bench so that a requirement misunderstanding does not reside in both. A code inspection

with the author, 1 or 2 senior engineers and 1 or 2 junior engineers helps ensure the code matches the

This phrase courtesy Jack Ganssle.

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2014 FPGA开发最佳实践：提升设计质量与效率

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