16-QAM Transmitter and Receiver Design Based on FPGA
Xuan-Thang Vu
Electronics& Telecommunication Faculty
College of Technology, VNU
Hanoi, Vietnam
thangvx@vnu.edu.vn
Nguyen Anh Duc
Electronics&Telecommunication Faculty
Hanoi University of Technology
Hanoi, Vietnam
ducnv-fet@mail.hut.edu.vn
Trinh Anh Vu
Electronics& Telecommunication Faculty
College of Technology, VNU
Hanoi, Vietnam
vuta@vnu.edu.vn
Abstract— The FPGA technology has been playing a
considerable role in portable and mobile communication. This
is due to the features of flexibility, accuracy and
configurability in designing and implementation. The paper
presents a complete design for a 16-QAM transmitter and
receiver based on the Virtex4 FPGA Kit. The implemented
system can be applied in particle. Based on the principles of
carrier synchronization, time synchronization, core tools for
phase-different detecting as well as adaptive equalization
processing in System Generator (a software of Xilinx), the
authors have designed a complete baseband IF 16-QAM
system, in which the baseband signal is upconverted into IF
frequency (up to 12MHz) at the transmitter and then is
downconverted at the receiver. After timing synchronizing, the
adaptive equalizing and phase recovering, the received
baseband signal is displayed in the oscilloscope’s screen. These
accurate experiments conducted in Virtex 4 FPGA board kit
have shown a promising foundation for developing coding,
algorithms in 16-QAM modulation scheme.
Keywords: FGPA design, Carrier Synchronization, Symbol
Recovery, 16-QAM Modulation.
I. INTRODUCTION
The development of mobile and portable
communications requires not only high performance of
hardware systems but also affectivity and flexibility in
design and implementation. In such situation, silicon
technology is one of the best choices which allow us to
produce high execution, high integrated density and
dedicated purpose integrated circuits (IC). However, silicon
solution is not sufficient for incessantly developing wireless
communication at the moment and in the future. Fortunately,
FPGA and ASIC technology has been merging as a suitable
selection for the next communication systems design. With
flexibility in design and precision in timing control, FPGA
makes it easier and more accurate in simulating, testing,
validating and implementing components. In addition,
system-level design which has being developed recently,
such as System Generator (Sysgen), makes design tasks
much easier than it has ever been before. Designers can
easily test algorithms, perform the whole system or modify
and update diagram shortly [1, 2, 3]. For this reason, system-
level design is playing a considerable role in designing and
implementing.
In communication, synchronization which consists of
both carrier and symbol level is the most challenging task.
There have been several researchers paying attention to solve
synchronization problem in particular, hence build a whole
communication system. The authors in [1] present a diagram
for carrier synchronization which uses phase-difference
detecting technique applied to QPSK signal, and the
principle of time recovery is mentioned as well. In [2], the
authors deal with the more challenging issues, say QAM
models. Because QAM signal has multiple amplitude levels,
a much more complex phase-difference detector is required.
The paper [5] provides a demo diagram for 16-QAM in
System Generator, which implements an adaptive equalizer
deploying LMS algorithm. However, this diagram is just fit
to a special phenomenon, thus cannot apply to practical
QAM systems.
In this paper, we present a diagram of a complete 16-
QAM scheme and the implementing results based on Xilinx
Virtex 4 FPGA Kit as well. The modulator and the
demodulator are performed in the two separated Kits. Both
carrier synchronization and symbol synchronization are
taken into account in this model using fast computing tool
(CORDIC) and LMS algorithm. The remaining of this paper
is presented as follow: section II denotes the demo diagram
for 16-QAM developed by [5], which consists of two
important bocks which are Adaptive Equalizer bock and
Carrier Recovery block. Section III states the 16-QAM
transmitter design. The most important part, the receiver, is
demonstrated in the section IV, and the implementing results
and conclusion are discussed in the section V.
II. A
BASE-BAND DEMODULATOR DEMO OF SYSTEM
GENERATOR [5]
The System Generator library provides a demo for 16-
QAM baseband demodulator which consists of two main
blocks: Adaptive Equalizer and Carrier Recovery (figure 1).
The Adaptive Equalizer operates based on LMS algorithm
and uses a 32-tap filter. Fast computing techniques using
CORDIC is employed to correct the phase error. This demo
uses a standard constellation as a training sequence. The
adaptive algorithm does work to minimize errors, hence
adjusts the constellation correct. However, because of these
features, this design can not be applied to deep fading
channels phenomenon
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications
978-0-7695-3978-2/10 $26.00 © 2010 IEEE
DOI 10.1109/DELTA.2010.34
95
2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications
978-0-7695-3978-2/10 $26.00 © 2010 IEEE
DOI 10.1109/DELTA.2010.34
95