TI高速FPD-Link解串器DS90UB901Q/DS90UB902Q：I2C接口与16位数据传输

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TI-DS90UB902Q-Q1是一款高性能的FPD-Link解串器，专为彩色显示器(FPD)接口的高速数据传输而设计。该设备提供两种型号，DS90UB901Q和DS90UB902Q，工作频率范围广泛，从10MHz到43MHz，支持高达688Mbps的数据吞吐量，适用于汽车摄像头系统与主机控制器或电子控制单元(Electronic Control Unit, ECU)之间的高速数据交互。 DS90UB901Q/DS90UB902Q的核心特性在于其包含一个高速正向数据通道，支持双向控制通道，以及一个内置I2C接口，可以直接与双向控制系统进行低延迟通信。这种设计使得数据传输不仅高效，而且能够在单个高速串行数据流中嵌入DC平衡编码的时钟信号，以支持AC耦合连接，确保16位图像数据的可靠传输。此外，该解串器还具备数据完整性选项，通过可选的CRC（循环冗余校验）功能来检测和纠正可能的传输链路错误，增强了数据的准确性。通过I2C兼容的接口，可以方便地控制GPIO，支持多达6个可编程通用输入输出，这些功能对于控制信号的处理非常重要。值得一提的是，DS90UB902Q支持在单个差分对上实现硬件级别的全双工通信，无需额外的数据完整性检查，这大大提高了数据传输的实时性和效率。同时，它能够驱动长达10米的屏蔽双绞线，即使在视频消隐间隔下，也能处理不对称双向控制信息，确保了长距离通信的稳定性能。这款解串器凭借其出色的性能、灵活性和可靠性，在现代汽车电子系统中扮演着关键角色，是构建高效、可靠视频数据链路的理想选择。欲了解更多详细规格和技术信息，可访问TI官方网站<www.ti.com.cn>查询相关文档，如ZHCSB01E-JUNE2010-REVISEDAPRIL2013。

DS90UB901Q, DS90UB902Q

www.ti.com.cn

ZHCSB01E –JUNE 2010–REVISED APRIL 2013

Electrical Characteristics

(1)(2)(3)

(continued)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

Differential Input Voltage

RIN+ - RIN- 180 mV

Range

Input Current V

= V

or 0V, V

= 1.89V -20 ±1 +20 µA

Differential Internal

Differential across RIN+ and RIN- 80 100 120 Ω

Termination Resistance

SER/DES SUPPLY CURRENT *DIGITAL, PLL, AND ANALOG VDD

DDT

= 100Ω

WORST CASE pattern 62 90

Serializer (Tx) VDDn = 1.89V

(Figure 5)

VDDn Supply Current PCLK = 43 MHz mA

= 100Ω

(includes load current) Default Registers

RANDOM PRBS-7 55

pattern

DDIOT

VDDIO = 1.89V

PCLK = 43 MHz 2 5

Serializer (Tx) R

= 100Ω

Default Registers

VDDIO Supply Current WORST CASE pattern mA

VDDIO = 3.6V

(includes load current) (Figure 5)

PCLK = 43 MHz 7 15

Default Registers

DDTZ

DDn

= 1.89V 370 775

Serializer (Tx) Supply PDB = 0V; All other

DDIOTZ

DDIO

= 1.89V 55 125 µA

Current Power-down LVCMOS Inputs = 0V

DDIO

= 3.6V 65 135

DDR

DDn

= 1.89V, C

= 8 pF PCLK = 43 MHz

WORST CASE Pattern, SSCG[3:0] = ON 60 96

Deserializer (Rx) VDDn

(Figure 5) Default Registers

Supply Current (includes

DDn

= 1.89V, C

= 8 pF

load current)

PCLK = 43 MHz

RANDOM PRBS-7 53

Default Registers

Pattern

DDIOR

DDIO

= 1.89V, C

= 8 pF

PCLK = 43 MHz

WORST CASE Pattern, 16 25

Deserializer (Rx) VDDIO

Default Registers

(Figure 5)

Supply Current (includes

load current)

DDIO

= 3.6V, C

= 8 pF PCLK = 43 MHz

38 64

WORST CASE Pattern Default Registers

DDRZ

DDn

= 1.89V 42 400

Deserializer (Rx) Supply PDB = 0V; All other

DDIORZ

DDIO

= 1.89V 8 40 µA

Current Power-down LVCMOS Inputs = 0V

DDIO

= 3.6V 350 800

DS90UB901Q, DS90UB902Q

ZHCSB01E –JUNE 2010–REVISED APRIL 2013

www.ti.com.cn

Recommended Serializer Timing for PCLK

(1)

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

TCP

Transmit Clock Period 23.3 T 100 ns

TCIH

Transmit Clock Input High

0.4T 0.5T 0.6T ns

Time

10 MHz – 43 MHz

TCIL

Transmit Clock Input Low

0.4T 0.5T 0.6T ns

Time

CLKT

PCLK Input Transition Time

0.5 3 ns

(Figure 11)

OSC

Internal oscillator clock

25 MHz

source

(1) Recommended Input Timing Requirements are input specifications and not tested in production.

Serializer Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Units

LHT

CML Low-to-High Transition

= 100Ω (Figure 6) 150 330 ps

Time

HLT

CML High-to-Low Transition

= 100Ω (Figure 6) 150 330 ps

Time

DIS

Data Input Setup to PCLK 2.0 ns

Serializer Data Inputs (Figure 12)

DIH

Data Input Hold from PCLK 2.0 ns

PLD

Serializer PLL Lock Time R

= 100Ω

(1)(2)

1 2 ms

= 100Ω, PCLK = 10–43 MHz

6.386T +

Serializer Delay Register 0x03h b[0] (TRFB = 1) 6.386T + 5 6.386T + 12 ns

19.7

(Figure 14)

JIND

Serializer output

intrinsic deterministic jitter .

Serializer Output Deterministic

Measured (cycle-cycle) with 0.13 UI

Jitter

PRBS-7 test pattern

PCLK = 43 MHz

(3)(4)

JINR

Serializer output intrinsic random

Serializer Output Random jitter (cycle-cycle). Alternating-1,0

0.04 UI

Jitter pattern.

PCLK = 43 MHz

(3)(4)

JINT

Serializer output peak-to-peak jitter

includes deterministic jitter,

random jitter, and jitter transfer

Peak-to-peak Serializer Output

from serializer input. Measured 0.396 UI

Jitter

(cycle-cycle) with PRBS-7 test

pattern.

PCLK = 43 MHz

(3)(4)

STXBW

Serializer Jitter Transfer PCLK = 43 MHz, Default Registers

1.90 MHz

Function -3 dB Bandwidth (Figure 20)

(3)

STX

Serializer Jitter Transfer PCLK = 43 MHz, Default Registers

0.944 dB

Function (Peaking) (Figure 20)

(3)

STXf

Serializer Jitter Transfer PCLK = 43 MHz, Default Registers

500 kHz

Function (Peaking Frequency) (Figure 20)

(3)

(1) t

PLD

and t

DDLT

is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active PCLK

(2) Specification is by design.

(3) Typical values represent most likely parametric norms at 1.8V or 3.3V, T

= +25°C, and at the Recommended Operation Conditions at

the time of product characterization and are not ensured.

(4) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.

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