TMS320C64x DSP内部双级内存指南

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"TMS320C64x DSP两层内部存储器参考指南" 《TMS320C64x DSP两层内部存储器参考指南》是德州仪器（Texas Instruments, TI）发布的一份技术文档，文学编号为SPRU610C，出版于2006年2月。这份资料主要针对TMS320C64x系列数字信号处理器（DSP）的内部存储结构进行了深入阐述，为设计者提供了详尽的内存使用和优化指导。 TMS320C64x DSP是一款高性能的数字信号处理器，其内部采用两层内存架构，旨在提高数据处理速度和效率。第一层通常包括高速缓存（Cache）和寄存器文件，用于存储频繁访问的数据，以减少外部存储器的访问延迟。第二层可能包括数据存储区和程序存储区，如RAM和ROM，用于存储程序代码和工作数据。文档中可能涵盖了以下关键知识点： 1. **内存组织**：详细介绍了两层内存的结构，包括它们的容量、访问速度和在处理器中的作用。 2. **存储器映射**：解释了如何将不同的内存区域映射到处理器地址空间，以及如何有效地管理这些区域。 3. **高速缓存操作**：包括缓存的填充策略、替换算法以及如何通过缓存优化数据访问性能。 4. **内存访问模式**：讨论了不同类型的内存访问，如单周期访问、多周期访问以及流水线访问。 5. **内存控制器**：阐述了内存控制器如何协调内外部存储器的交互，确保数据流的连续性。 6. **编程模型**：指导开发人员如何在C64x DSP上编写高效代码，利用内存层次结构进行优化。 7. **性能评估**：可能包含了一些实例分析，展示了不同内存配置对系统整体性能的影响。 8. **应用示例**：可能提供了一些典型的应用场景，帮助读者理解如何在实际项目中应用这些内存特性。 9. **警告与免责声明**：TI强调，尽管他们为产品性能提供标准保修，但不承担应用程序协助或客户产品设计的责任。用户应负责自己的产品和应用设计，并在下单前确认最新的产品信息。此外，TI还指出，他们可能会随时对产品和服务进行修正、修改、增强或改进，且有权无通知地停止任何产品或服务。因此，用户在使用TMS320C64x DSP时，应始终关注最新的技术支持文档，以确保所使用的信息是最新的、完整的。《TMS320C64x DSP两层内部存储器参考指南》是设计和优化基于TMS320C64x DSP系统的重要参考资料，它为开发者提供了必要的工具和知识，以充分利用该处理器的内存架构，提升系统性能。

Cache Terms and Definitions

TMS320C64x Two-Level Internal Memory

SPRU610C

Table 2. Terms and Definitions (Continued)

Term Definition

DMA Direct Memory Access. Typically, a DMA operation copies a block of memory from

one range of addresses to another, or transfers data between a peripheral and

memory. On the C64x DSP, DMA transfers are performed by the enhanced DMA

(EDMA) engine. These DMA transfers occur in parallel to program execution. From a

cache coherence standpoint, EDMA accesses can be considered accesses by a

parallel processor.

Eviction The process of removing a line from the cache to make room for newly cached data.

Eviction can also occur under user control by requesting a writeback-invalidate for an

address or range of addresses from the cache. The evicted line is referred to as the

victim. When a victim line is dirty (that is, it contains updated data), the data must be

written out to the next level memory to maintain coherency.

Execute packet A block of instructions that begin execution in parallel in a single cycle. An execute

packet may contain between 1 and 8 instructions.

Fetch packet A block of 8 instructions that are fetched in a single cycle. One fetch packet may

contain multiple execute packets, and thus may be consumed over multiple cycles.

First-reference miss A cache miss that occurs on the first reference to a piece of data. First-reference

misses are a form of compulsory miss.

Fully-associative

cache

A cache that allows any memory address to be stored at any location within the

cache. Such caches are very flexible, but usually not practical to build in hardware.

They contrast sharply with direct-mapped caches and set-associative caches, both of

which have much more restrictive allocation policies. Conceptually, fully-associative

caches are useful for distinguishing between conflict misses and capacity misses

when analyzing the performance of a direct-mapped or set-associative cache. In

terms of set-associative caches, a fully-associative cache is equivalent to a

set-associative cache that has as many ways as it does line frames, and that has

only one set.

Higher-level memory In a hierarchical memory system, higher-level memories are memories that are

closer to the CPU. The highest level in the memory hierarchy is usually the Level 1

caches. The memories at this level exist directly next to the CPU. Higher-level

memories typically act as caches for data from lower-level memory.

Hit

A cache hit occurs when the data for a requested memory location is present in the

cache. The opposite of a hit is a miss. A cache hit minimizes stalling, since the data

can be fetched from the cache much faster than from the source memory. The

determination of hit versus miss is made on each level of the memory hierarchy

separately—a miss in one level may hit in a lower level.

Cache Terms and Definitions

TMS320C64x Two-Level Internal MemorySPRU610C

Table 2. Terms and Definitions (Continued)

Term Definition

Invalidate The process of marking valid cache lines as invalid in a particular cache. Alone, this

action discards the contents of the affected cache lines, and does not write back any

updated data. When combined with a writeback, this effectively updates the next

lower level of memory that holds the data, while completely removing the cached

data from the given level of memory. Invalidates combined with writebacks are

referred to as writeback-invalidates, and are commonly used for retaining coherence

between caches.

Least Recently Used

(LRU) allocation

For set-associative and fully-associative caches, least-recently used allocation refers

to the method used to choose among line frames in a set when allocating space in

the cache. When all of the line frames in the set that the address maps to contain

valid data, the line frame in the set that was read or written the least recently (furthest

back in time) is selected to hold the newly cached data. The selected line frame is

then evicted to make room for the new data.

Line A cache line is the smallest block of data that the cache operates on. The cache line

is typically much larger than the size of data accesses from the CPU or the next

higher level of memory. For instance, although the CPU may request single bytes

from memory, on a read miss the cache reads an entire line’s worth of data to satisfy

the request.

Line frame A location in a cache that holds cached data (one line), an associated tag address,

and status information for the line. The status information can include whether the

line is valid, dirty, and the current state of that line’s LRU.

Line size The size of a single cache line, in bytes.

Load through When a CPU request misses both the first-level and second-level caches, the data is

fetched from the external memory and stored to both the first-level and second-level

cache simultaneously. A cache that stores data and sends that data to the

upper-level cache at the same time is a load-through cache. Using a load-through

cache reduces the stall time compared to a cache that first stores the data in a lower

level and then sends it to the higher-level cache as a second step.

Long-distance access Accesses made by the CPU to a noncacheable memory. Long-distance accesses

are used when accessing external memory that is not marked as cacheable.

Lower-level memory In a hierarchical memory system, lower-level memories are memories that are further

from the CPU. In a C64x system, the lowest level in the hierarchy includes the

system memory below L2 and any memory-mapped peripherals.

LRU

Least Recently Used. See least recently used allocation for a description of the LRU

replacement policy. When used alone, LRU usually refers to the status information

that the cache maintains for identifying the least-recently used line in a set. For

example, consider the phrase “accessing a cache line updates the LRU for that line.”

Cache Terms and Definitions

TMS320C64x Two-Level Internal Memory

SPRU610C

Table 2. Terms and Definitions (Continued)

Term Definition

Memory ordering Defines what order the effects of memory operations are made visible in memory.

(This is sometimes referred to as consistency.) Strong memory ordering at a given

level in the memory hierarchy indicates it is not possible to observe the effects of

memory accesses in that level of memory in an order different than program order.

Relaxed memory ordering allows the memory hierarchy to make the effects of

memory operations visible in a different order. Note that strong ordering does not

require that the memory system execute memory operations in program order, only

that it makes their effects visible to other requestors in an order consistent with

program order. Section 8.3 covers the memory ordering assurances that the C64x

memory hierarchy provides.

Miss A cache miss occurs when the data for a requested memory location is not in the

cache. A miss may stall the requestor while the line frame is allocated and data is

fetched from the next lower level of memory. In some cases, such as a CPU write

miss from L1D, it is not strictly necessary to stall the CPU. Cache misses are often

divided into three categories: compulsory misses, conflict misses, and capacity

misses.

Miss pipelining The process of servicing a single cache miss is pipelined over several cycles. By

pipelining the miss, it is possible to overlap the processing of several misses, should

many occur back-to-back. The net result is that much of the overhead for the

subsequent misses is hidden, and the incremental stall penalty for the additional

misses is much smaller than that for a single miss taken in isolation.

Read allocate A read-allocate cache only allocates space in the cache on a read miss. A write miss

does not cause an allocation to occur unless the cache is also a write-allocate cache.

For caches that do not write allocate, the write data would be passed on to the next

lower-level cache.

Set A collection of line frames in a cache that a single address can potentially reside. A

direct-mapped cache contains one line frame per set, and an N-way set-associative

cache contains N line frames per set. A fully-associative cache has only one set that

contains all of the line frames in the cache.

Set-associative

cache

A set-associative cache contains multiple line frames that each lower-level memory

location can be held in. When allocating room for a new line of data, the selection is

made based on the allocation policy for the cache. The C64x devices employ a least

recently used allocation policy for its set-associative caches.

Snoop

A method by which a lower-level memory queries a higher-level memory to

determine if the higher-level memory contains data for a given address. The primary

purpose of snoops is to retain coherency, by allowing a lower-level memory to

request updates from a higher-level memory. A snoop operation may trigger a

writeback, or more commonly, a writeback-invalidate. Snoops that trigger

writeback-invalidates are sometimes called snoop-invalidates.

Cache Terms and Definitions

TMS320C64x Two-Level Internal MemorySPRU610C

Table 2. Terms and Definitions (Continued)

Term Definition

Tag A storage element containing the most-significant bits of the address stored in a

particular line. Tag addresses are stored in special tag memories that are not directly

visible to the CPU. The cache queries the tag memories on each access to

determine if the access is a hit or a miss.

Thrash An algorithm is said to thrash the cache when its access pattern causes the

performance of the cache to suffer dramatically. Thrashing can occur for multiple

reasons. One possible situation is that the algorithm is accessing too much data or

program code in a short time frame with little or no reuse. That is, its working set is

too large, and thus the algorithm is causing a significant number of capacity misses.

Another situation is that the algorithm is repeatedly accessing a small group of

different addresses that all map to the same set in the cache, thus causing an

artificially high number of conflict misses.

Touch A memory operation on a given address is said to touch that address. Touch can also

refer to reading array elements or other ranges of memory addresses for the sole

purpose of allocating them in a particular level of the cache. A CPU-centric loop used

for touching a range of memory in order to allocate it into the cache is often referred

to as a touch loop. Touching an array is a form of software-controlled prefetch for data.

Valid When a cache line holds data that has been fetched from the next level memory, that

line frame is valid. The invalid state occurs when the line frame holds no data, either

because nothing has been cached yet, or because previously cached data has been

invalidated for whatever reason (coherence protocol, program request, etc.). The

valid state makes no implications as to whether the data has been modified since it

was fetched from the lower-level memory; rather, this is indicated by the dirty or

clean state of the line.

Victim When space is allocated in a set for a new line, and all of the line frames in the set

that the address maps to contain valid data, the cache controller must select one of

the valid lines to evict in order to make room for the new data. Typically, the

least-recently used (LRU) line is selected. The line that is evicted is known as the

victim line. If the victim line is dirty, its contents are written to the next lower level of

memory using a victim writeback.

Victim Buffer A special buffer that holds victims until they are written back. Victim lines are moved

to the victim buffer to make room in the cache for incoming data.

Victim Writeback When a dirty line is evicted (that is, a line with updated data is evicted), the updated

data is written to the lower levels of memory. This process is referred to as a victim

writeback.

Way

In a set-associative cache, each set in the cache contains multiple line frames. The

number of line frames in each set is referred to as the number of ways in the cache.

The collection of corresponding line frames across all sets in the cache is called a

way in the cache. For instance, a 4-way set-associative cache has 4 ways, and each

set in the cache has 4 line frames associated with it, one associated with each of the

4 ways. As a result, any given cacheable address in the memory map has 4 possible

locations it can map to in a 4-way set-associative cache.

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