DDR4内存子系统中的CAB4A缓冲器技术详解

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"TI-CAB4A.pdf 是一款由德州仪器(TI)推出的DDR4内存子系统中的关键组件，主要用于CPU、DSP、Ethernet MCU等内存控制器与内存模块之间的信号传输和处理。该文档详细介绍了CAB4A DDR4寄存器的功能、特性以及其在DDR4 RDIMM和LRDIMM内存模块中的应用。" TI-CAB4A是一款专为DDR4内存设计的32位1:2命令/地址/控制缓冲器和1:4差分时钟缓冲器。它符合DDR4 RCD01JEDEC标准，适用于在1.2V VDD工作模式下运行的DDR4双列直插内存模块，包括RDIMM和LRDIMM，以及3D堆叠DIMM应用。这款器件的关键特性包括： 1. **兼容性**：CAB4A完全符合DDR4 RCD01JEDEC标准，确保了与DDR4内存系统的兼容性。 2. **32位1:2命令/地址/控制缓冲**：该器件可以将32位的输入信号分成两路输出，增强了信号传输的稳定性和效率。 3. **1:4差分时钟缓冲**：提供四个时钟输出，支持低负载的DDR4 DIMM，优化了15Ω至50Ω有效端接迹线的性能。 4. **内部PLL**：集成的锁相环(PLL)具有内部反馈功能，可调整时钟频率，适应不同速度的DDR4内存模块。 5. **可配置输出驱动器**：输出驱动器强度可调，能补偿不同DIMM网状拓扑结构的需求，同时支持扩展弱驱动器功能。 6. **输入/输出管理**：输入通过CK_t变为高电平和CK_c变为低电平交叉点被捕捉，输出驱动器可以校准，地址映射和倒置功能允许灵活的系统配置。 7. **编程延迟**：CAB4A支持编程延迟，能够在CK_t和CK_c的不同时钟频率下运行，提高了系统时序的灵活性。 8. **伪差分输入**：所有输入都可以使用外部或内部电压基准，增强了抗噪声能力。 TI-CAB4A是DDR4内存系统中的关键组件，它优化了命令、地址、控制信号和时钟信号的传输，确保了高速、低延迟和可靠的内存操作。对于设计高性能、低功耗的计算平台，如服务器、数据中心或高端嵌入式系统，CAB4A是不可或缺的一部分。

CAB4A

www.ti.com.cn

ZHCSBP1B –JULY 2013–REVISED OCTOBER 2013

Table 1. TERMINAL FUNCTIONS

SIGNAL

TYPE DESCRIPTION

GROUP NAME

DCKE0/1 DRAM corresponding register function pins not associated with

DODT0/1 Chip Select.

DCS0_n..DCS1_

DRAM corresponding register Chip Select signals.

DRAM corresponding register Chip Select signals. These pins

initiate DRAM address/command decodes, and as such exactly

Input Control bus CMOS

(1)

VREF based

DCS2_n..DCS3_

one will be LOW when a valid address/command is present

which should be re-driven.

Some of these have alternative functions:

DC0..DC1

• DCS2_n ↔ DC0

• DCS3_n ↔ DC1

DC2 DRAM corresponding register Chip ID 2 signal.

DRAM corresponding register inputs. In case of an ACT

command some of these terminals have an alternative

function:

DA0..DA13,

DRAM corresponding register command signals

DA17

DBA0..DBA1,

• DA14 ↔ DWE_n

DBG0..DBG1

• DA15 ↔ DCAS_n

CMOS

(1)

VREF based

Input Address and

• DA16 ↔ DRAS_n

Command bus

DA14..DA16

DWE_n,

DCAS_n,

DRAS_n

DACT_n DRAM corresponding register DACT_n signal.

Differential master clock input pair to the PLL with a 10 kΩ ~

Clock inputs CK_t, CK_c CMOS differential

100 kΩ pull-down resistor.

Active LOW asynchronous reset input. When LOW, it causes a

Reset input DRST_n CMOS input reset of the internal latches and disables the outputs, thereby

forcing the outputs to float.

Input parity is received on pin DPAR and should maintain even

Parity input DPAR CMOS

(2)

VREF based parity across the address and command inputs (see above), at

the rising edge of the input clock.

DRAM address parity and CRC Alert is connected to this input

Error Input ERROR_IN_n CMOS input pin, which in turn is buffered and re-driven to the ALERT_n

output of the register. Requires external pull-up resistor.

(3)

BODT Data buffer on-die termination signal.

BCKE Data buffer clock enable signal for PLL power management.

CMOS

(3)

Data buffer control

and communication BCOM[3:0]

control access.

outputs

BCK_t, BCK_c CMOS differential Differential clock output pair to the data buffer

BVREFCA VDD/2Reference Voltage Output reference voltage for data buffer control bus receivers.

(1) These receivers use VREFCA as the switching point reference.

(2) These receivers use VREFCA as the switching point reference.

(3) CMOS: These outputs with rail to rail signal swing and programmable impedance are optimized for memory applications to drive DRAM

inputs over a terminated transmission line.

Error_In_n: Internal Pull-up resistor can be turned on.

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