PCIe 4.0规格审查：交易描述符和改进需求

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本文档主要关注的是PCIe (Peripheral Component Interconnect Express) 4.0规范的更新，特别是针对开放性问题进行讨论的部分。PCIe 4.0标准旨在提升数据传输速度和带宽，以满足现代计算系统对高速I/O连接的需求。在阅读这份文档时，我们注意到以下几个关键要点： 1. **Transaction Descriptor中的Transaction ID Field and Tags**: - 标签字段（Tag field）当前长度为8位，但随着一些实施者已接近256个同时 outstanding read请求的极限，可能需要扩展。考虑的解决方案包括： - 修改phantom functions的定义 - 重新利用BE (Bus Error) 字段 - 在Length字段、Type或其他字段中编码 - 使用保留位 - 利用TLV (Type-Length-Value) 前缀 - 同时，完成头（Completion header）中可能需要增加一个互补字段，如字节数或更低地址，以保持一致性。 2. **FC Header Credits的数量**: - PCIe 4.0规范规定，每接收端最多可以累积2047个未使用的信用给发送端用于数据包载荷，或者127个信用用于FC (Flow Control) 头。为了适应更高带宽，可能需要提高这个限制，但具体数值尚未确定。 3. **Flow Control (FC) Information**: - 文档在多个章节（Section 2.6.1的第三点、Section 2.6.1.1和2.6.1.2）详细讨论了FC规则，强调了数据链路层（Section 3.4.1）的协议要求，这些规则可能在升级到4.0时需要调整以支持更大的数据流量控制。 4. **其他潜在变化**: - 文档还提到可能涉及其他方面的更改，但具体内容没有详细列出，这部分需要进一步分析和讨论。这份PCIe 4.0规范修订草案中，主要关注的是交易描述符字段的扩展、FC相关限制的调整以及可能的协议优化，以应对更高的性能需求。阅读时，开发人员和设计工程师应密切关注这些变化，确保他们的设计符合新的规范要求。随着技术的发展，未来可能会有更多关于带宽管理、错误处理和兼容性的讨论。

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.5

9.3.5 Tx Jitter Parameters ............................................................................................... 998

9.3.6 Tx and Rx Return Loss .......................................................................................... 1008

9.3.7 Transmitter PLL Bandwidth and Peaking ............................................................ 1009

9.3.8 Data Rate Independent Tx Parameters ................................................................. 1010

9.4 RECEIVER SPECIFICATIONS ........................................................................................ 1011

9.4.1 Receiver Stressed Eye Specification ..................................................................... 1011

9.4.2 Stressed Eye Test ................................................................................................... 1017

9.4.3 Common Receiver Parameters ............................................................................. 1022

9.4.4 Low Frequency and Miscellaneous Signaling Requirements ............................... 1025

9.5 CHANNEL TOLERANCING ........................................................................................... 1027

9.5.1 Channel Compliance Testing ................................................................................ 1027

9.6 REFCLK SPECIFICATIONS ........................................................................................... 1036

9.6.1 Refclk Test Setup ................................................................................................... 1036

9.6.2 Data Rate Independent Refclk Parameters ........................................................... 1037

9.6.3 Refclk Architectures Supported ............................................................................. 1038

9.6.4 Filtering Functions Applied to Raw Data ............................................................. 1038

9.6.5 Common Refclk Rx Architecture (CC) .................................................................. 1040

9.6.6 Jitter Limits for Refclk Architectures .................................................................... 1042

10 SR-IOV SPECIFICATION ............................................................................................ 1043

11 ATS SPECIFICATION .................................................................................................. 1044

A. ISOCHRONOUS APPLICATIONS ................................................................................. 1046

A.1. INTRODUCTION .......................................................................................................... 1046

A.2. ISOCHRONOUS CONTRACT AND CONTRACT PARAMETERS ......................................... 1048

A.2.1. Isochronous Time Period and Isochronous Virtual Timeslot ........................... 1049

A.2.2. Isochronous Payload Size ................................................................................. 1050

A.2.3. Isochronous Bandwidth Allocation ................................................................... 1050

A.2.4. Isochronous Transaction Latency ..................................................................... 1051

A.2.5. An Example Illustrating Isochronous Parameters ............................................ 1052

A.3. ISOCHRONOUS TRANSACTION RULES ......................................................................... 1053

A.4. TRANSACTION ORDERING .......................................................................................... 1053

A.5. ISOCHRONOUS DATA COHERENCY ............................................................................. 1053

A.6. FLOW CONTROL ......................................................................................................... 1054

A.7. CONSIDERATIONS FOR BANDWIDTH ALLOCATION ..................................................... 1054

A.7.1. Isochronous Bandwidth of PCI Express Links.................................................. 1054

A.7.2. Isochronous Bandwidth of Endpoints ............................................................... 1054

A.7.3. Isochronous Bandwidth of Switches ................................................................. 1054

A.7.4. Isochronous Bandwidth of Root Complex......................................................... 1055

A.8. CONSIDERATIONS FOR PCI EXPRESS COMPONENTS ................................................... 1055

A.8.1. An Endpoint as a Requester .............................................................................. 1055

A.8.2. An Endpoint as a Completer ............................................................................. 1055

A.8.3. Switches............................................................................................................. 1056

A.8.4. Root Complex .................................................................................................... 1057

B. SYMBOL ENCODING .................................................................................................... 1058

C. PHYSICAL LAYER APPENDIX .................................................................................... 1067

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.5

C.1. 8B/10B DATA SCRAMBLING EXAMPLE ....................................................................... 1067

C.2. 128B/130B DATA SCRAMBLING EXAMPLE ................................................................. 1073

D. REQUEST DEPENDENCIES .......................................................................................... 1076

E. ID-BASED ORDERING USAGE .................................................................................... 1079

E.1. INTRODUCTION .......................................................................................................... 1079

E.2. POTENTIAL BENEFITS WITH IDO USE ........................................................................ 1080

E.2.1. Benefits for MFD/RP Direct Connect ............................................................... 1080

E.2.2. Benefits for Switched Environments ................................................................. 1080

E.2.3. Benefits for Integrated Endpoints ..................................................................... 1081

E.2.4. IDO Use in Conjunction with RO ..................................................................... 1081

E.3. WHEN TO USE IDO .................................................................................................... 1081

E.4. WHEN NOT TO USE IDO ............................................................................................ 1082

E.4.1. When Not to Use IDO with Endpoints .............................................................. 1082

E.4.2. When Not to Use IDO with Root Ports ............................................................. 1082

E.5. SOFTWARE CONTROL OF IDO USE ............................................................................. 1083

E.5.1. Software Control of Endpoint IDO Use ............................................................ 1083

E.5.2. Software Control of Root Port IDO Use ........................................................... 1084

F. MESSAGE CODE USAGE .............................................................................................. 1085

G. PROTOCOL MULTIPLEXING ................................................................................... 1087

G.1. PROTOCOL MULTIPLEXING INTERACTIONS WITH PCI EXPRESS ................................. 1090

G.2. PMUX PACKETS ........................................................................................................ 1096

G.3. PMUX PACKET LAYOUT ........................................................................................... 1097

G.3.1. PMUX Packet Layout for 8b10b Encoding ...................................................... 1097

G.3.2. PMUX Packet Layout at 128b/130b Encoding ................................................. 1099

G.4. PMUX CONTROL ....................................................................................................... 1102

G.5. PMUX EXTENDED CAPABILITY ................................................................................. 1102

G.5.1. PCI Express Extended Header (Offset 00h) ..................................................... 1103

G.5.2. PMUX Capability Register (Offset 04h) ........................................................... 1104

G.5.3. PMUX Control Register (Offset 08h) ............................................................... 1105

G.5.4. PMUX Status Register (Offset 0Ch) ................................................................. 1107

G.5.5. PMUX Protocol Array (Offsets 10h Through 48h) .......................................... 1110

H. M-PCIE TIMING DIAGRAMS .................................................................................... 1112

H.1. INIT TO L0 .................................................................................................................. 1113

H.2. L0 WITH TRANSMITTER IN STALL ............................................................................ 1114

H.3. L0 TO L1 .................................................................................................................... 1115

H.4. DOWNSTREAM PORT INITIATED LINK BANDWIDTH CHANGE ................................... 1116

H.5. UPSTREAM PORT INITIATED LINK BANDWIDTH CHANGE ......................................... 1117

I. M-PCIE COMPLIANCE PATTERNS ......................................................................... 1118

I.1. RPAT ........................................................................................................................ 1118

I.2. RPAT VARIATION BY LANE ...................................................................................... 1119

I.3. CONTINUOUS MODE CRPAT ..................................................................................... 1119

I.4. BURST MODE CRPAT ............................................................................................... 1120

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.5

Figures

FIGURE 1-1: PCI EXPRESS LINK .................................................................................................... 53

FIGURE 1-2: EXAMPLE TOPOLOGY ................................................................................................ 54

FIGURE 1-3: LOGICAL BLOCK DIAGRAM OF A SWITCH ................................................................. 58

FIGURE 1-4: HIGH-LEVEL LAYERING DIAGRAM ........................................................................... 60

FIGURE 1-5: PACKET FLOW THROUGH THE LAYERS ..................................................................... 61

FIGURE 2-1: LAYERING DIAGRAM HIGHLIGHTING THE TRANSACTION LAYER .............................. 66

FIGURE 2-2: SERIAL VIEW OF A TLP ............................................................................................. 69

FIGURE 2-3: GENERIC TLP FORMAT ............................................................................................. 70

FIGURE 2-4: FIELDS PRESENT IN ALL TLPS .................................................................................. 71

FIGURE 2-5: FIELDS PRESENT IN ALL TLP HEADERS .................................................................... 72

FIGURE 2-6: EXAMPLES OF COMPLETER TARGET MEMORY ACCESS FOR FETCHADD ................... 77

FIGURE 2-7: 64-BIT ADDRESS ROUTING ........................................................................................ 79

FIGURE 2-8: 32-BIT ADDRESS ROUTING ........................................................................................ 79

FIGURE 2-9: ID ROUTING WITH 4 DW HEADER ............................................................................ 81

FIGURE 2-10: ID ROUTING WITH 3 DW HEADER .......................................................................... 82

FIGURE 2-11: LOCATION OF BYTE ENABLES IN TLP HEADER ....................................................... 83

FIGURE 2-12: TRANSACTION DESCRIPTOR .................................................................................... 85

FIGURE 2-13: TRANSACTION ID .................................................................................................... 86

FIGURE 2-14: ATTRIBUTES FIELD OF TRANSACTION DESCRIPTOR ................................................ 88

FIGURE 2-15: REQUEST HEADER FORMAT FOR 64-BIT ADDRESSING OF MEMORY ........................ 92

FIGURE 2-16: REQUEST HEADER FORMAT FOR 32-BIT ADDRESSING OF MEMORY ........................ 92

FIGURE 2-17: REQUEST HEADER FORMAT FOR I/O TRANSACTIONS .............................................. 93

FIGURE 2-18: REQUEST HEADER FORMAT FOR CONFIGURATION TRANSACTIONS ........................ 94

FIGURE 2-19: TPH TLP PREFIX .................................................................................................... 95

FIGURE 2-20: LOCATION OF PH[1:0] IN A 4 DW REQUEST HEADER ............................................. 95

FIGURE 2-21: LOCATION OF PH[1:0] IN A 3 DW REQUEST HEADER ............................................. 96

FIGURE 2-22: LOCATION OF ST[7:0] IN THE MEMORY WRITE REQUEST HEADER ......................... 97

FIGURE 2-23: LOCATION OF ST[7:0] IN MEMORY READ AND ATOMICOP REQUEST HEADERS ..... 97

FIGURE 2-24: MESSAGE REQUEST HEADER .................................................................................. 99

FIGURE 2-25: HEADER FOR VENDOR-DEFINED MESSAGES ......................................................... 109

FIGURE 2-26: HEADER FOR PCI-SIG-DEFINED VDMS ................................................................ 110

FIGURE 2-27: LN MESSAGE ......................................................................................................... 112

FIGURE 2-28: DRS MESSAGE ...................................................................................................... 113

FIGURE 2-29: FRS MESSAGE ...................................................................................................... 114

FIGURE 2-30: LTR MESSAGE ...................................................................................................... 116

FIGURE 2-31: OBFF MESSAGE ................................................................................................... 117

FIGURE 2-32: PTM REQUEST/RESPONSE MESSAGE ..................................................................... 118

FIGURE 2-33: PTM RESPONSED MESSAGE (4 DW HEADER AND 1 DW PAYLOAD) ...................... 119

FIGURE 2-34: COMPLETION HEADER FORMAT ............................................................................ 120

FIGURE 2-35: (NON-ARI) COMPLETER ID .................................................................................. 121

FIGURE 2-36: ARI COMPLETER ID .............................................................................................. 121

FIGURE 2-37: FLOWCHART FOR HANDLING OF RECEIVED TLPS ................................................. 128

FIGURE 2-38: FLOWCHART FOR SWITCH HANDLING OF TLPS ..................................................... 130

PCI EXPRESS BASE SPECIFICATION, REV. 4.0 VERSION 0.5

FIGURE 2-39: FLOWCHART FOR HANDLING OF RECEIVED REQUEST ........................................... 135

FIGURE 2-40: VIRTUAL CHANNEL CONCEPT – AN ILLUSTRATION .............................................. 152

FIGURE 2-41: VIRTUAL CHANNEL CONCEPT – SWITCH INTERNALS (UPSTREAM FLOW) ............. 152

FIGURE 2-42: AN EXAMPLE OF TC/VC CONFIGURATIONS .......................................................... 155

FIGURE 2-43: RELATIONSHIP BETWEEN REQUESTER AND ULTIMATE COMPLETER ..................... 156

FIGURE 2-44: CALCULATION OF 32-BIT ECRC FOR TLP END TO END DATA INTEGRITY

PROTECTION ........................................................................................................................ 172

FIGURE 3-1: LAYERING DIAGRAM HIGHLIGHTING THE DATA LINK LAYER ................................ 180

FIGURE 3-2: DATA LINK CONTROL AND MANAGEMENT STATE MACHINE .................................. 183

FIGURE 3-3: VC0 FLOW CONTROL INITIALIZATION EXAMPLE WITH 8B/10B ENCODING-BASED

FRAMING ............................................................................................................................. 188

FIGURE 3-4: DLLP TYPE AND CRC FIELDS ................................................................................ 189

FIGURE 3-5: DATA LINK LAYER PACKET FORMAT FOR ACK AND NAK ....................................... 191

FIGURE 3-6: DATA LINK LAYER PACKET FORMAT FOR INITFC1 ................................................ 191

FIGURE 3-7: DATA LINK LAYER PACKET FORMAT FOR INITFC2 ................................................ 191

FIGURE 3-8: DATA LINK LAYER PACKET FORMAT FOR UPDATEFC ............................................ 192

FIGURE 3-9: PM DATA LINK LAYER PACKET FORMAT ............................................................... 192

FIGURE 3-10: VENDOR SPECIFIC DATA LINK LAYER PACKET FORMAT ...................................... 192

FIGURE 3-11: DIAGRAM OF CRC CALCULATION FOR DLLPS ..................................................... 193

FIGURE 3-12: TLP WITH LCRC AND TLP SEQUENCE NUMBER APPLIED ................................... 194

FIGURE 3-13: TLP FOLLOWING APPLICATION OF TLP SEQUENCE NUMBER AND RESERVED BITS

............................................................................................................................................. 196

FIGURE 3-14: CALCULATION OF LCRC ...................................................................................... 198

FIGURE 3-15: RECEIVED DLLP ERROR CHECK FLOWCHART ...................................................... 206

FIGURE 3-16: ACK/NAK DLLP PROCESSING FLOWCHART .......................................................... 207

FIGURE 3-17: RECEIVE DATA LINK LAYER HANDLING OF TLPS ................................................ 211

FIGURE 4-1: LAYERING DIAGRAM HIGHLIGHTING PHYSICAL LAYER .......................................... 217

FIGURE 4-2: CHARACTER TO SYMBOL MAPPING ......................................................................... 218

FIGURE 4-3: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X1 EXAMPLE ............................ 219

FIGURE 4-4: BIT TRANSMISSION ORDER ON PHYSICAL LANES - X4 EXAMPLE ............................ 219

FIGURE 4-5: TLP WITH FRAMING SYMBOLS APPLIED ................................................................. 222

FIGURE 4-6: DLLP WITH FRAMING SYMBOLS APPLIED .............................................................. 223

FIGURE 4-7: FRAMED TLP ON A X1 LINK .................................................................................... 223

FIGURE 4-8: FRAMED TLP ON A X2 LINK .................................................................................... 224

FIGURE 4-9: FRAMED TLP ON A X4 LINK .................................................................................... 224

FIGURE 4-10: LFSR WITH SCRAMBLING POLYNOMIAL ............................................................... 226

FIGURE 4-11: EXAMPLE OF BIT TRANSMISSION ORDER IN A X1 LINK SHOWING 130 BITS OF A

BLOCK ................................................................................................................................. 227

FIGURE 4-12: EXAMPLE OF BIT PLACEMENT IN A X4 LINK WITH ONE BLOCK PER LANE ............ 227

FIGURE 4-13: LAYOUT OF FRAMING TOKENS .............................................................................. 231

FIGURE 4-14: TLP AND DLLP LAYOUT ...................................................................................... 233

FIGURE 4-15: PACKET TRANSMISSION IN A X8 LINK ................................................................... 233

FIGURE 4-16: NULLIFIED TLP LAYOUT IN A X8 LINK WITH OTHER PACKETS ............................. 234

FIGURE 4-17: SKP ORDERED SET OF LENGTH 66-BIT IN A X8 LINK ............................................ 234

FIGURE 4-18: LFSR WITH SCRAMBLING POLYNOMIAL IN 8.0 GT/S AND ABOVE DATA RATE .... 242

FIGURE 4-19: ALTERNATE IMPLEMENTATION OF THE LFSR FOR DESCRAMBLING ...................... 244

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