RISC架构详解：MIPS、Alpha等CPU的独特指令集

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本篇文档是《计算机组织与设计》（Computer Organization and Design）附录E的内容，由Steven Przybylski撰写，版权属于2013年Elsevier Inc.。该附录详细探讨了RISC（Reduced Instruction Set Computing）架构在桌面、服务器和嵌入式计算机中的应用，时间点是在1985年RISC概念提出之后。 RISC架构是针对简化指令集设计的计算机体系结构，其主要目标是提高处理器性能和执行效率，通过减少指令集的复杂性和数量来实现。附录E按章节展开，从介绍开始，逐步深入： 1. **介绍**：阐述了RISC架构的发展背景和设计理念，以及它如何在不同类型的计算机系统中发挥作用。 2. **地址模式与指令格式**：讲解了RISC架构中常见的地址寻址方式和指令格式设计，这些是理解处理器工作原理的基础。 3. **MIPS核心子集**：以斯坦福MIPS为例，介绍了RISC架构的核心指令集，包括基本的数据处理和控制指令。 4. **多媒体扩展**：讨论了针对桌面和服务器RISC处理器的多媒体扩展，如处理音频和视频数据的专用指令。 5. **数字信号处理扩展**：特别关注嵌入式RISC在数字信号处理应用中的定制指令，提高处理速度和功耗效率。 6. **MIPS核心通用扩展**：涵盖了对其他技术的集成，如加密、浮点运算等，增强核心指令集的功能。 7. **MIPS-64的独特指令**：专为64位计算设计的MIPS特定指令集，支持更大的内存操作和数据类型。 8. **Alpha、SPARCv9、PowerPC、PA-RISC、ARM、Thumb、SuperH和M32R的独特指令**：分别针对不同厂商的RISC架构，列举了各自特有的高级特性或扩展指令。 9. **MIPS-16和MIPS-16E**：可能涉及两种不同版本或子集的MIPS指令集。 10. **结论性评论**：总结了RISC架构在各种计算机系统中的影响，强调了其灵活性和适应性，以及在不断变化的技术环境中持续的重要性。通过这个附录，读者可以深入了解RISC架构的设计思想，并了解其在不同应用场景中的具体实现细节。这对于计算机硬件设计者、系统架构师以及深入理解计算机体系结构的学生来说，是一份宝贵的参考资料。

E.3 Instructions: the MIPS Core Subset E-9

Figures E.2.5 and E.2.6 show the variations in extending constant  elds to the

full width of the registers. In this subtle point, the RISCs are similar but not

identical.

E.3 Instructions: the MIPS Core Subset

 e similarities of each architecture allow simultaneous descriptions, starting with

the operations equivalent to the MIPS core.

MIPS Core Instructions

Almost every instruction found in the MIPS core is found in the other

architectures, as Figures E.3.1 through E.3.5 show. (For reference, de nitions of the

MIPS instructions are found in the MIPS Reference Data Card at the beginning

of the book.) Instructions are listed under four categories: data transfer (Figure

E.3.1); arithmetic/logical (Figure E.3.2); control (Figure E.3.3); and  oating point

(Figure E.3.4). A   h category (Figure E.3.5) shows conventions for register

Format: instruction category Alpha MIPS-64 PA-RISC 2.0 PowerPC SPARCv9

ngiSngiSngiSngiSngiSlla:hcnarB

ngiSngiSngiS—ngiSlla:llac/pmuJ

ngiSoreZ—oreZoreZlacigol:etaidemmi-retsigeR

FIGURE E.2.5 Summary of constant extension for desktop RISCs.  e constants in the jump and call instructions of MIPS

are not sign-extended, since they only replace the lower 28 bits of PC, leaving the upper 4 bits unchanged. PA-RISC has no logical immediate

instructions.

Format: instruction category Armv4 Thumb SuperH M32R MIPS-16

ngiS ngiS ngiS ngiS ngiS lla :hcnarB

— ngiS ngiS oreZ/ngiS ngiS lla :llac/pmuJ

— oreZ oreZ — oreZlacigol :etaidemmi-retsigeR

FIGURE E.2.6 Summary of constant extension for embedded RISCs.  e 16-bit-length instructions have much shorter

immediates than those of the desktop RISCs, typically only  ve to eight bits. Most embedded RISCs, however, have a way to get a long address

for procedure calls from two sequencial halfwords.  e constants in the jump and call instructions of MIPS are not sign-extended, since they

only replace the lower 28 bits of the PC, leaving the upper 4 bits unchanged.  e 8-bit immediates in ARM can be rotated right an even number

of bits between 2 and 30, yielding a large range of immediate values. For example, all powers of two are immediates in ARM.

E-10 Appendix E A Survey of RISC Architectures

Data transfer

(instruction formats)

R-I R-I R-I, R-R R-I, R-R R-I, R-R

Instruction name Alpha MIPS-64 PA-RISC 2.0 PowerPC SPARCv9

Load byte signed

LDBU; SEXTB LB LDB; EXTRW,S 31,8 LBZ; EXTSB LDSB

Load byte unsigned

LDBU LBU LDB, LDBX, LDBS LBZ LDUB

Load halfword signed

LDWU; SEXTW LH LDH; EXTRW,S 31,16 LHA LDSH

Load halfword unsigned

LDWU LHU LDH, LDHX, LDHS LHZ LDUH

Load word

LDLS LW LDW, LDWX, LDWS LW LD

Load SP ﬂ oat

LDS

LWC1 FLDWX, FLDWS LFS LDF

Load DP ﬂ oat

LDT LDC1 FLDDX, FLDDS LFD LDDF

Store byte

STB SB STB, STBX, STBS STB STB

Store halfword

STW SH STH, STHX, STHS STH STH

Store word

STL SW STW, STWX, STWS STW ST

Store SP ﬂ oat

STS SWC1 FSTWX, FSTWS STFS STF

Store DP ﬂ oat

STT SDC1 FSTDX, FSTDS STFD STDF

Read, write special registers

MF_, MT_ MF, MT_ MFCTL, MTCTL MFSPR, MF_,

MTSPR, MT_

RD, WR, RDPR, WRPR,

LDXFSR, STXFSR

Move integer to FP register

ITOFS MFC1/DMFC1 STW; FLDWX STW; LDFS ST; LDF

Move FP to integer register

FTTOIS MTC1/DMTC1 FSTWX; LDW STFS; LW STF; LD

FIGURE E.3.1 Desktop RISC data transfer instructions equivalent to MIPS core. A sequence of instructions to synthesize a

MIPS instruction is shown separated by semicolons. If there are several choices of instructions equivalent to MIPS core, they are separated

by commas. For this  gure, halfword is 16 bits and word is 32 bits. Note that in Alpha, LDS converts single precision  oating point to double

precision and loads the entire 64-bit register.

usage and pseudoinstructions on each architecture. If a MIPS core instruction

requires a short sequence of instructions in other architectures, these instructions

are separated by semicolons in Figures E.3.1 through E.3.5. (To avoid confusion,

the destination register will always be the le most operand in this appendix,

independent of the notation normally used with each architecture.) Figures E.3.6

through E.3.9 show the equivalent listing for embedded RISCs. Note that  oating

point is generally not de ned for the embedded RISCs.

Every architecture must have a scheme for compare and conditional branch, but

despite all the similarities, each of these architectures has found a di erent way to

perform the operation.

Compare and Conditional Branch

SPARC uses the traditional four condition code bits stored in the program status

word: negative, zero, carry, and over ow.  ey can be set on any arithmetic or logical

instruction; unlike earlier architectures, this setting is optional on each instruction.

An explicit option leads to fewer problems in pipelined implementation. Although

condition codes can be set as a side e ect of an operation, explicit compares are

synthesized with a subtract using r0 as the destination. SPARC conditional branches

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RISC架构详解：MIPS、Alpha等CPU的独特指令集

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