S5P6818芯片最新手册：应用处理器详解

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SAMSUNG S5P6818是一款应用处理器，其详细规格和技术文档在本手册中得到了详尽的阐述。此版本为0.00修订版，发布于2015年2月，旨在供学习和理解该芯片内部结构、功能以及设计者使用。手册由Samsung Electronics Co., Ltd.原创并保留所有版权，用户只能用于参考目的。 S5P6818芯片的主要特点是高性能处理能力，它可能包含多种核心架构，如Cortex-A或ARM内核，用于执行各种计算密集型任务。手册涵盖了芯片的技术特性，如处理器频率、内存接口、外部接口规范（如USB、UART、GPIO等）、多媒体处理单元（如图像处理、音频解码等）以及安全特性等。重要通知部分强调了Samsung对手册内容拥有随时修改的权利，且用户使用其中的信息仅需参考，不得用于商业用途，也不承担因使用手册内容产生的任何错误或遗漏所导致的责任。此外，Samsung明确表示其产品并非针对特定用途设计，不提供任何形式的产品担保，包括但不限于质量保证，特别是对于由于应用或使用造成的任何间接或附带损害，Samsung概不负责。购买和使用S5P6818芯片的开发者或制造商需要自行确保产品的适用性和安全性，这意味着在设计和实施系统时，他们需要根据手册中的指导进行充分的测试和验证，并了解潜在的风险和限制。为了深入理解和使用这款芯片，开发人员应仔细阅读手册的硬件和软件接口章节，学习如何配置、编程和调试。此外，还应注意查看任何更新版本的手册，因为随着技术的发展，Samsung可能会发布新的补丁或优化，以解决已知问题和提升性能。 S5P6818芯片手册是设计者和工程师的宝贵资源，提供了关于该处理器的关键信息，但使用者必须遵守版权规定和责任声明，以确保正确和安全地应用到实际项目中。

Samsung Confidential

34 MULTI LAYER CONTROLLER (MLC) ...................................................... 34-1

34.1 Overview .............................................................................................................................................. 34-1

34.2 Features ............................................................................................................................................... 34-2

34.3 Block Diagram ...................................................................................................................................... 34-3

34.4 Dual Register Set Architecture............................................................................................................. 34-4

34.5 MLC Global Parameters ...................................................................................................................... 34-5

34.5.1 Screen Size .................................................................................................................................. 34-6

34.5.2 Priority ........................................................................................................................................... 34-6

34.5.3 Field Mode .................................................................................................................................... 34-7

34.5.4 Background Color ......................................................................................................................... 34-7

34.5.5 Per-layer Parameters ................................................................................................................... 34-8

34.5.6 Enable ......................................................................................................................................... 34-10

34.5.7 Lock Control ................................................................................................................................ 34-10

34.5.8 Position ....................................................................................................................................... 34-11

34.5.9 Pixel Format ................................................................................................................................ 34-12

34.5.10 Address Generation .................................................................................................................. 34-17

34.5.11 Video Layer Specific Parameters ............................................................................................. 34-19

34.5.12 Scale Function .......................................................................................................................... 34-20

34.5.13 Gamma Correction ................................................................................................................... 34-26

34.6 Clock Generation ............................................................................................................................... 34-27

34.7 Register Description ........................................................................................................................... 34-28

34.7.1 Register Map Summary .............................................................................................................. 34-28

35 DISPLAY CONTROLLER (DPC) ............................................................... 35-1

35.1 Overview .............................................................................................................................................. 35-1

35.2 Features ............................................................................................................................................... 35-1

35.3 Block Diagram ...................................................................................................................................... 35-2

35.4 Sync Generator .................................................................................................................................... 35-3

35.4.1 Clock Generation .......................................................................................................................... 35-4

35.4.2 Format .......................................................................................................................................... 35-7

35.4.3 Sync Signals ............................................................................................................................... 35-11

35.4.4 Scan Mode .................................................................................................................................. 35-18

35.4.5 Delay ........................................................................................................................................... 35-18

35.4.6 Interrupt ...................................................................................................................................... 35-19

35.4.7 MPU (i80) Type Sync Signals ..................................................................................................... 35-20

35.4.8 Odd/Even Field Flag ................................................................................................................... 35-22

35.4.9 Internal Video encoder and DAC ................................................................................................ 35-23

35.5 Register Description ........................................................................................................................... 35-30

35.5.1 Register Map Summary .............................................................................................................. 35-30

36 DE-INTERLACE ........................................................................................ 36-1

36.1 Overview .............................................................................................................................................. 36-1

36.2 Features ............................................................................................................................................... 36-1

36.3 Operation ............................................................................................................................................. 36-2

36.3.1 Even Operation ............................................................................................................................. 36-2

36.3.2 Odd Operation .............................................................................................................................. 36-3

36.3.3 Y, Cb, Cr Operation ...................................................................................................................... 36-4

36.3.4 De-Interlace Operation Flow ......................................................................................................... 36-5

36.4 Register Description ............................................................................................................................. 36-6

36.4.1 Register Map Summary ................................................................................................................ 36-6

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37 SCALER .................................................................................................... 37-1

37.1 Overview .............................................................................................................................................. 37-1

37.2 Features ............................................................................................................................................... 37-1

37.3 Block Diagram ...................................................................................................................................... 37-2

37.4 Functional Description ......................................................................................................................... 37-3

37.4.1 Digital Filter Characteristics .......................................................................................................... 37-3

37.5 Programming Guide ............................................................................................................................. 37-5

37.5.1 Configuration ................................................................................................................................ 37-5

37.5.2 RUN .............................................................................................................................................. 37-6

37.6 Register Description ............................................................................................................................. 37-7

37.6.1 Register Map Summary ................................................................................................................ 37-7

38 LVDS ......................................................................................................... 38-1

38.1 Overview .............................................................................................................................................. 38-1

38.2 Features ............................................................................................................................................... 38-1

38.3 Block Diagram ...................................................................................................................................... 38-2

38.4 Functional Description ......................................................................................................................... 38-3

38.4.1 LVDS Data Packing Format ......................................................................................................... 38-3

38.4.2 LVDS Application Note ................................................................................................................. 38-4

38.4.3 Skew Control between Output Data and Clock ............................................................................ 38-5

38.4.4 Electrical Characteristics .............................................................................................................. 38-6

38.5 Register Description ............................................................................................................................. 38-7

38.5.1 Register Map Summary ................................................................................................................ 38-7

38.5.2 DisplayTop Register ................................................................................................................... 38-18

39 HDMI .......................................................................................................... 39-1

39.1 Overview .............................................................................................................................................. 39-1

39.2 Features ............................................................................................................................................... 39-1

39.3 Block Diagram ...................................................................................................................................... 39-2

39.4 Functional Description ......................................................................................................................... 39-3

39.4.1 Select RGB Video data for HDMI ................................................................................................. 39-3

39.4.2 HDMI Converter ............................................................................................................................ 39-3

39.4.3 HDMI LINK .................................................................................................................................... 39-5

39.5 Register Description ........................................................................................................................... 39-16

39.5.1 Register Map Summary .............................................................................................................. 39-16

39.6 HDMI PHY ........................................................................................................................................ 39-152

39.6.1 PHY Configuration Change through APB ................................................................................. 39-152

39.6.2 PHY Ready Sequence .............................................................................................................. 39-153

39.6.3 HDMI PHY Configuration .......................................................................................................... 39-154

39.6.4 Register Description ................................................................................................................. 39-156

40 MIPI ........................................................................................................... 40-1

40.1 Overview .............................................................................................................................................. 40-1

40.2 Features ............................................................................................................................................... 40-2

40.2.1 DSI Master Features (DSIM) ........................................................................................................ 40-2

40.2.2 CSI Slave Features (CSIS) ........................................................................................................... 40-2

40.3 D-PHY Features ................................................................................................................................... 40-3

40.4 Block Diagram for DSIM ...................................................................................................................... 40-4

40.4.1 Internal Primary FIFOs ................................................................................................................. 40-5

40.4.2 Packet Header Arbitration ............................................................................................................ 40-5

40.4.3 RxFIFO Structure.......................................................................................................................... 40-6

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40.5 Interfaces and Protocol ........................................................................................................................ 40-7

40.5.1 Display Controller Interface .......................................................................................................... 40-7

40.5.2 RGB Interface ............................................................................................................................... 40-8

40.5.3 HSA Mode .................................................................................................................................... 40-8

40.5.4 HSE Mode .................................................................................................................................. 40-10

40.5.5 Transfer General Data in Video Mode ........................................................................................ 40-11

40.5.6 MIPI DSIM Converts RGB Interface to Video Mode ................................................................... 40-12

40.6 Configuration ...................................................................................................................................... 40-13

40.7 PLL ..................................................................................................................................................... 40-13

40.8 Buffer .................................................................................................................................................. 40-13

40.9 DSIM .................................................................................................................................................. 40-14

40.9.1 Register Description ................................................................................................................... 40-14

40.10 CSIS ................................................................................................................................................. 40-38

40.10.1 Interfaces and Protocol ............................................................................................................. 40-38

40.10.2 Configuration ............................................................................................................................ 40-43

40.10.3 Interrupt .................................................................................................................................... 40-43

40.10.4 Clock Specification ................................................................................................................... 40-44

40.10.5 Register Description ................................................................................................................. 40-45

40.11 D-PHY .............................................................................................................................................. 40-57

40.11.1 Architecture ............................................................................................................................... 40-57

41 VIDEO INPUT PROCESSOR (VIP)............................................................ 41-1

41.1 Overview .............................................................................................................................................. 41-1

41.2 Features ............................................................................................................................................... 41-1

41.3 Block Diagram ...................................................................................................................................... 41-2

41.4 VIP Interconnection .............................................................................................................................. 41-3

41.4.1 Block Diagram .............................................................................................................................. 41-3

41.4.2 Clock Generation .......................................................................................................................... 41-4

41.4.3 Sync Generation ........................................................................................................................... 41-4

41.4.4 External Data Valid and Field ....................................................................................................... 41-9

41.4.5 Data Order .................................................................................................................................. 41-10

41.4.6 Status .......................................................................................................................................... 41-11

41.4.7 FIFO Controls ............................................................................................................................. 41-11

41.4.8 Recommend Setting for Video Input Port ................................................................................... 41-12

41.5 Clipper & Decimator ........................................................................................................................... 41-13

41.5.1 Clipping & Scale-down ............................................................................................................... 41-13

41.5.2 Output Data Format .................................................................................................................... 41-15

41.5.3 Interlace Scan Mode ................................................................................................................... 41-16

41.5.4 Pixels Alignment ......................................................................................................................... 41-16

41.6 Interrupt Generation ........................................................................................................................... 41-17

41.7 Register Description ........................................................................................................................... 41-18

41.7.1 Register Map Summary .............................................................................................................. 41-18

42 MULTI-FORMAT VIDEO CODEC .............................................................. 42-1

42.1 Overview .............................................................................................................................................. 42-1

42.2 Functional Description ......................................................................................................................... 42-2

42.2.1 List of Video CODECs .................................................................................................................. 42-2

42.2.2 Supported Video Encoding Tools ................................................................................................. 42-3

42.2.3 Supported Video Decoding Tools ................................................................................................. 42-4

42.2.4 Supported JPEG Tools ................................................................................................................. 42-5

42.2.5 Non-codec related features .......................................................................................................... 42-6

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43 3D GRAPHIC ENGINE .............................................................................. 43-1

43.1 Overview .............................................................................................................................................. 43-1

43.2 Features ............................................................................................................................................... 43-2

43.2.1 Pixel Processor Features ............................................................................................................. 43-2

43.2.2 Geometry Processor Features ..................................................................................................... 43-2

43.2.3 Level 2 Cache Controller Features ............................................................................................... 43-3

43.2.4 MMU ............................................................................................................................................. 43-3

43.2.5 PMU .............................................................................................................................................. 43-3

43.3 Operation ............................................................................................................................................. 43-4

43.3.1 Clock ............................................................................................................................................. 43-4

43.3.2 Reset ............................................................................................................................................ 43-4

43.3.3 Interrupt ........................................................................................................................................ 43-4

44 CRYPTO ENGINE ..................................................................................... 44-1

44.1 Overview .............................................................................................................................................. 44-1

44.2 Features ............................................................................................................................................... 44-1

44.3 Block Diagram ...................................................................................................................................... 44-2

44.4 Functional Description ......................................................................................................................... 44-4

44.4.1 Polling Mode ................................................................................................................................. 44-4

44.4.2 Mode ............................................................................................................................................. 44-4

44.5 Register Description ............................................................................................................................. 44-5

44.5.1 Register Map Summary ................................................................................................................ 44-5

45 SECURE JTAG .......................................................................................... 45-1

45.1 Overview .............................................................................................................................................. 45-1

45.2 Features ............................................................................................................................................... 45-1

45.3 Block Diagram ...................................................................................................................................... 45-2

45.4 Secure JTAG User Configure .............................................................................................................. 45-2

46 TEMPERATURE MONITOR UNIT (TMU) .................................................. 46-1

46.1 Overview .............................................................................................................................................. 46-1

46.2 Temperature Sensing Auto Mode with External Clocks ...................................................................... 46-3

46.3 Temperature Code Table ..................................................................................................................... 46-4

46.4 I/O Description ..................................................................................................................................... 46-6

46.5 Programming Guide ............................................................................................................................. 46-9

46.5.1 Software Sequence .................................................................................................................... 46-10

46.5.2 Interrupt Service Routine ............................................................................................................ 46-11

46.5.3 Tracing Past Temperature .......................................................................................................... 46-12

46.6 Register Description ........................................................................................................................... 46-13

46.6.1 Register Map Summary .............................................................................................................. 46-13

47 ELECTRICAL CHARACTERISTICS .......................................................... 47-1

47.1 Absolute Maximum Ratings ................................................................................................................. 47-1

47.2 Recommended Operating Conditions .................................................................................................. 47-2

47.3 D.C. Electrical Characteristics ............................................................................................................. 47-4

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List of Figures

Figure Title Page

Number Number

Figure 1-1 Block Diagram ................................................................................................................................... 1-3

Figure 2-1 Mechanical Dimension - Top, Side, Bottom View ............................................................................. 2-1

Figure 2-2 Mechanical Dimension - Dimension Value ....................................................................................... 2-2

Figure 2-3 FCBGA Ball Map (Top View) ............................................................................................................ 2-3

Figure 2-4 FCBGA Ball Map (Top View) - Upper Left Side ................................................................................ 2-4

Figure 2-5 FCBGA Ball Map (Top View) - Upper Right Side ............................................................................. 2-5

Figure 2-6 FCBGA Ball Map (Top View) - Lower Left Side ................................................................................ 2-6

Figure 2-7 FCBGA Ball Map (Top View) - Lower Right Side ............................................................................. 2-7

Figure 3-1 External Static Memory Boot ............................................................................................................ 3-5

Figure 3-2 SPI ROM Boot Operation ................................................................................................................. 3-7

Figure 3-3 UART Boot Operation ....................................................................................................................... 3-8

Figure 3-4 USB Boot Operation ......................................................................................................................... 3-9

Figure 3-5 SDHC Boot Operation .................................................................................................................... 3-12

Figure 3-6 NANDBOOTEC Operation .............................................................................................................. 3-14

Figure 4-1 Block Diagram ................................................................................................................................... 4-2

Figure 4-2 Block Diagram of PLL ....................................................................................................................... 4-3

Figure 4-3 CPU Clock ...................................................................................................................................... 4-11

Figure 4-4 System BUS Clock.......................................................................................................................... 4-12

Figure 4-8 System BUS Clock.......................................................................................................................... 4-13

Figure 4-5 System BUS Clock.......................................................................................................................... 4-14

Figure 4-6 System BUS Clock.......................................................................................................................... 4-14

Figure 4-7 Power Management Sequence ...................................................................................................... 4-16

Figure 4-8 Power Down Mode Sequence ........................................................................................................ 4-18

Figure 4-9 Wake Up Block Diagram ................................................................................................................. 4-19

Figure 4-10 Power-On Reset Sequence .......................................................................................................... 4-20

Figure 4-11 Power On Sequence for Wakeup ................................................................................................. 4-22

Figure 4-12 Power Off Sequence ..................................................................................................................... 4-23

Figure 4-13 Example Implementation of ProgQoS Control Registers for 2  1 Interconnect .......................... 4-26

Figure 4-14 Example Operation of RR Arbitration Scheme ............................................................................. 4-28

Figure 5-1 Interconnection Example of Clock Generator ................................................................................... 5-1

Figure 5-2 Block Diagram of Clock Generator Level 0 ...................................................................................... 5-2

Figure 5-3 Block Diagram of Clock Generator Level 1 ...................................................................................... 5-7

Figure 5-4 Block Diagram of Clock Generator Level 2 .................................................................................... 5-19

Figure 6-1 Example Implementation of ProgQoS Control Registers for 2x1 Interconnect ................................ 6-2

Figure 8-1 System L2 Cache Block Diagram ..................................................................................................... 8-3

Figure 9-1 DMAC Block Diagram ....................................................................................................................... 9-3

Figure 9-2 LLI Example .................................................................................................................................... 9-16

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