IEEE 1450-1999标准扩展：STIL测试流程规格语言

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IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) 是一项由IEEE计算机协会的测试技术标准委员会赞助的重要标准，它最初是为测试流程规范设计的。该标准定义了STIL，这是一种用于描述和执行自动化测试过程的标准语言，它允许测试生成工具与测试设备之间进行有效的通信，从而提高测试的效率和一致性。 1999年的IEEE Std 1450-1999在测试自动化领域起到了基石的作用，然而随着技术的发展和需求的变化，随着时间的推移，标准需要扩展以适应新的测试环境和工具。因此，后续版本的IEEE Std 1450.4™-2017应运而生，它对原标准进行了增强和完善。 IEEE Std 1450.4™-2017在保持原有STIL核心概念的基础上，可能增加了新的功能特性、性能指标、接口协议或者兼容性支持，以便更好地满足现代测试场景的需求，如云计算、大数据驱动的测试、分布式测试架构等。例如，它可能包含了对自动化测试框架的集成，对智能测试用例管理的支持，或者对故障模拟和回归测试的自动化描述。该标准的批准日期为2017年12月6日，由IEEE-SA Standards Board正式确认，这表明其经过了严格的审查和标准化过程，确保了其技术先进性和实用性。然而，使用该标准的授权受限，仅限于特定机构，如UNIVERSITY OF SUSSEX，下载自IEEE Explore时可能受到版权和使用限制。 IEEE Std 1450 for Test Flow Specification 的扩展标准旨在通过持续更新和完善，为测试工程师提供一个更加灵活且功能强大的工具，以支持他们在复杂系统和快速变化的技术环境中进行有效和高效的测试工作。这不仅提高了测试的质量，也促进了测试行业的标准化和互操作性。

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IEEE Std 1450.4-2017

IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for Test Flow

Specification

1.2 Scope

This standard specifies extensions to STIL.0 that define the description of certain test flow and binning

components of an integrated circuit (IC) test program in a test-hardware-independent manner. These

extensions provide language constructs and semantics necessary to describe both the test program flow and

the sequencing data needed to compose a test program to run on an automated test equipment (ATE)

platform. The language constructs defined include structures for specifying the following:

 Order of execution of test program components

 Hierarchical test flow structures to facilitate automated modification or maintenance

 Common interfaces between the test flow environment and test program components

 Test flow variables to facilitate concurrent and serial test flow interactions

 Binning or categorization of tested ICs

The following aspects integral to test execution are specifically not addressed by this standard:

 The standardization of the interface between the prober or handler and tester is beyond the scope of

STIL.4. STIL.4 requires that appropriate AsynchronousEvent signals shall be issued to the

TestProgram triggering the corresponding entry-points.

 Input/output operations and exception handling.

 The definition of TestMethods is beyond the scope of this standard.

1.3 Purpose

STIL is the standard for the interchange of digital test data from the test generation environment (where a

great deal of design information is used to generate device tests) to the test and manufacturing environment.

The initial STIL standard (IEEE Std 1450-1999) addresses the essential digital test description information

(i.e., signals, timing, vectors, and parameter specifications). Other aspects needed for testing devices are

provided in extension activities such as this standard, which addresses test flow extensions to STIL.

The flow and binning constructs in this extension allow for developing a test program description in a

common language; this common description can either be used as input to a test program generator that

translates the description into the native language of specific IC ATE systems or be run directly on IC ATE

systems that use IEEE 1450.4 as their native language.

2. Normative references

The following referenced documents are indispensable for the application of this document (i.e., they must

be understood and used, so each referenced document is cited in text and its relationship to this document is

explained). For dated references, only the edition cited applies. For undated references, the latest edition of

the referenced document (including any amendments or corrigenda) applies.

IEEE Std 754™-2008, Standard for Floating-Point Arithmetic.

2,3

IEEE Std 1450™-1999, IEEE Standard Test Interface Language (STIL) for Digital Test Vector Data.

The IEEE standards or products referred to in Clause 2 are trademarks owned by The Institute of Electrical and Electronics

Engineers, Incorporated.

IEEE publications are available from The Institute of Electrical and Electronics Engineers (http://standards.ieee.org/).

This standard combined with IEEE Std 1450.2 and IEEE Std 1450.4 can be used to describe the minimum information required to

generate a test program, i.e., timing, levels, patterns, and flow.

Authorized licensed use limited to: UNIVERSITY OF SUSSEX. Downloaded on May 05,2018 at 10:36:36 UTC from IEEE Xplore. Restrictions apply.

IEEE Std 1450.4-2017

IEEE Standard for Extensions to Standard Test Interface Language (STIL) (IEEE Std 1450-1999) for Test Flow

Specification

IEEE Std 1450.1™-2005, Extensions to STIL for Semiconductor Design Environments.

IEEE Std 1450.2™-2002, Extensions to STIL for for DC Level Specification.

IEEE Std 1450.3™-2007, Extensions to STIL for Tester Target Specification.

3. Definitions, abbreviations, and acronyms

3.1 Definitions

For the purposes of this document, the following terms and definitions apply. The IEEE Standards

Dictionary Online should be consulted for terms not defined in this clause.

anonymous: A term to describe an element that has no name/identifier.

assign: To modify the value of an existing instantiation. Value none is not legal.

actions: A general term for a syntax subset constrained to specific test, flow, and flow-node sub-blocks.

The syntax controls flow via commands that assign, compare, or evaluate variables; set or clear soft bins;

and stop program execution.

argument: An expression used to initialize a parameter.

attribute: Ancillary information attached to an object or type describing a property.

buffer: A term to describe a chip interface design cell accessible via a pad.

channel: A physical conduit connecting a tester resource, usually via a tester pin. A channel provides

access to, e.g., power, ground, a driver, comparator, control bit.

chip: An instance of a device design on, or cut from, a wafer.

Components: When capitalized, a keyword referring to electrical components such as resistors or

capacitors usually mounted on a load-board.

Const: When capitalized, a keyword used as a modifier to denote a variable that represents a single value

during normal execution of the test program.

constraint: A special kind of attribute that narrows assignment options.

die: A device design that may be replicated on a wafer in the form of individual chips.

flow or Flow: A general term or, when capitalized, a keyword for a collection of FlowNodes. In

FlowExtended mode, a Flow can be viewed as a special kind of test.

flow-node: A general term for a node in a directed graph represented by keyword FlowNode.

This standard combined with IEEE Std 1450 and IEEE Std 1450.4 can be used to describe the minimum information required to

generate a test program, i.e., timing, levels, patterns, and flow.

This standard may be used to impose specific target tester limitations on timing, levels, and patterns.

IEEE Standards Dictionary Online subscription is available at http://dictionary.ieee.org.

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