Atmel AVR 8位微控制器ATMEGA169PA-AU技术规格

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"ATMEGA169PA-AU是一款由Atmel公司生产的8位微控制器，具有16/32/64K字节的在系统可编程闪存，适用于低功耗、高性能的应用场景。" ATMEGA169PA-AU是Atmel AVR系列的成员，该系列以其高效能、低功耗的特性而闻名。这款微控制器基于先进的RISC（精简指令集计算）架构，设计有130条强大的指令，大多数指令可以在单个时钟周期内执行，极大地提高了处理速度。在16MHz的工作频率下，它可以达到每秒16百万条指令（MIPS）的吞吐量，而在20MHz下，对于某些型号如ATmega329PA，可以达到每秒20MIPS的性能。在存储方面，ATMEGA169PA-AU提供了不同容量的非易失性内存（Flash程序存储器），具体分为16K字节（ATmega169A/ATmega169PA）、32K字节（ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA）以及64K字节（ATmega649A/ATmega649P/ATmega6490A/ATmega6490P）。此外，它还配备了EEPROM存储，容量分别为512字节（ATmega169A/ATmega169PA）、1K字节（ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA）和2K字节（ATmega649A/ATmega649P/ATmega6490A/ATmega6490P）。这些内存均支持在系统自编程功能，允许程序在运行过程中进行更新。内部的SRAM（静态随机访问存储器）也根据不同型号提供了1K字节（ATmega169A/ATmega169PA）、2K字节（ATmega329A/ATmega329PA/ATmega3290A/ATmega3290PA）或4K字节（ATmega649A/ATmega649P/ATmega6490A/ATmega6490P）的空间，用于存储运行时的数据。写入/擦除周期长达10,000次对于Flash，100,000次对于EEPROM，确保了长时间的稳定使用。数据保持能力为在85°C环境下20年，在25°C环境下100年，保证了数据的安全存储。这些特性使得ATMEGA169PA-AU适用于各种需要高效能和低功耗运算的嵌入式系统应用，例如工业控制、物联网设备、智能家居、汽车电子以及便携式设备等。其丰富的内存配置和高处理速度使其能够灵活应对不同规模和复杂度的项目需求。

8284D–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

7.5.1 The X-register, Y-register, and Z-register

The registers R26...R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 7-3.

Figure 7-3. The X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see the instruction set reference for details).

7.6 Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. Note that the Stack is implemented as

growing from higher to lower memory locations. The Stack Pointer Register always points to the

top of the Stack. The Stack Pointer points to the data SRAM Stack area where the Subroutine

and Interrupt Stacks are located. A Stack PUSH command will decrease the Stack Pointer.

The Stack in the data SRAM must be defined by the program before any subroutine calls are

executed or interrupts are enabled. Initial Stack Pointer value equals the last address of the

internal SRAM and the Stack Pointer must be set to point above start of the SRAM, see Figure

8-2 on page 21.

See Table 7-1 for Stack Pointer details.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 70 7 0

R31 (0x1F) R30 (0x1E)

Table 7-1. Stack Pointer instructions

Instruction Stack pointer Description

PUSH Decremented by 1 Data is pushed onto the stack

CALL

ICALL

RCALL

Decremented by 2

Return address is pushed onto the stack with a subroutine call or

interrupt

POP Incremented by 1 Data is popped from the stack

RET

RETI

Incremented by 2 Return address is popped from the stack with return from

subroutine or return from interrupt

8284D–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

7.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate program vector in the program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt. Depending on the Program

Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12

are programmed. This feature improves software security. See the section ”Memory Program-

ming” on page 310 for details.

The lowest addresses in the program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 56. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL

bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 56 for more information.

The Reset Vector can also be moved to the start of the Boot Flash section by programming the

BOOTRST Fuse, see ”Boot Loader Support – Read-While-Write Self-Programming” on page

294.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a

Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the

Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-

tor in order to execute the interrupt handling routine, and hardware clears the corresponding

Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)

to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is

cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is

cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt

Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the

Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

8284D–AVR–6/11

ATmega169A/PA/329A/PA/3290A/PA/649A/P/6490A/P

CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence.

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

7.8.1 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clock cycles the program vector address for the actual interrupt handling routine

is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt

execution response time is increased by four clock cycles. This increase comes in addition to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock

cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is

incremented by two, and the I-bit in SREG is set.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

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