2QW-Clock: An efficient SSD buffer management
algorithm
Dan He
1, 2
, Fang Wang
1
, Dan Feng
1
, Jing Ning Liu
1
, Yun Xiang Wu
1
,Yang Hu
3
,Ying He
1,2
1
Wuhan National Laboratory for Optoelectronics, Wuhan, China
School of Computer Science and Technology, Huazhong University of Science and Technology, Wuhan, China
2
School of Information Engineering, Nanchang Hangkong University, Nanchang, China
3
China Ship Development & Design Center, Wuhan, China
Corresponding author :{ wangfang, jnliu}@hust.edu.cn,
{hdnchu, dfeng, yxwu, heying}@hust.edu.cn, yanghu@foxmail.com
Abstract—Modern solid state disk (SSD) has a buffer (SDRAM),
which is used to store commonly used data and map in the near
future. How to efficient management of this buffer is an
important things of improving performance of SSD. Flash read
and write speed have asymmetric characteristic. SSD buffer
management algorithms must consider this characteristic of flash.
Current page mapping SSD buffer management algorithms
mainly use the Clean-First LRU (CFLRU) algorithm to first
replace the clean buffer pages regardless of whether these pages
will soon be used in the near future. At the same time, LRU
buffer management algorithm of SSD does not consider file
scanning. In order to solve these problems, we proposes a new
SSD internal buffer management algorithm, called Two Queue
Weight-Clock (2QW-Clock). This algorithm combines the
advantages of 2Q and gives different weights to read page and
write page to reflect the asymmetry of flash read and write speed.
Therefore, it can get high write page hit ratios while maintaining
high total page hit ratios. With the high write ratios, 2QW-Clock
reduces the numbers of SSD write and erase operations. So it can
greatly extend the life of the SSD. Conducting simulations with a
variety of traces and a wide range of buffer sizes, we show that
2QW-Clock write hit ratios are significantly higher than CFLRU,
LRU and 2Q in most cases while total hit ratios are almost as the
2Q. Simulation result shows that the numbers of 2QW-Clock
write and erase counts reduced by up to 30% less than that of 2Q
and CFLRU.
Keywords-SSD; flash; replacement algorithm; buffer
management
I. INTRODUCTION
A. Background
With the decline of flash price, SSD which use flash
storage medium have been widely used in high-end servers
and notebook computers. SSD usually consists of the
following components: flash chips, flash translation layer
(FTL), flash controller and internal SDRAM, as shown in
Figure. 1. There are two types of flash chip, NOR flash and
NAND flash. NOR flash support random access with byte
level, but its price is higher than NAND flash, and its
integration is lower than NAND flash, so chips of SSD most
commonly use NAND flash. NAND flash chips have
asymmetrical features in read and write, and the read speeds
are approximately 8~12 times faster than the write speeds,
such as the Samsung K9XXG08UXA series chip reading time
is 25 µs and writing time is 200 µs [1]. The store unit for
NAND-flash chip is page and block. Each block contains
several pages. The unit of read and write is page. The content
of page must be erased before write. The erase unit is block
and the write numbers are limited. At present, single SLC
(single-level cell) flash write/erase (P/E) number of times
around 100k, 2-bit MLC flash write/erase (P/E) number of
times 3k [2, 3, 4], 3-bit MLC flash write/erase (P/E) number
only hundreds of times [5]. So we should minimize the
number of write to improve the life of SSD, which is
necessary to improve the hit ratios for SSD, especially the
write hit ratios. The high hit ratios can also improve the SSD
throughput and reduce the SSD read and write response time.
File system
Read operation
(begin address size)
Write operation
(begin addressˈsize)
SSD
block block block block block
page
page
page
Read
operation
Write
operation
Erase
operation
FTL
Address mapping
Wear Leveling
Garbage collection
SDRAM
Internal structure of ssd
FLASH
controler
Figure 1. Structure of SSD
B. The Function of FTL Layer
Because the operating system is developed for the disk
(Hard Disk) and SSD structure and disk structure are not the
same, this requires an intermediate transition layer to hide
SSD features which can let the operating system uses SSD just
like HDD. The intermediate is FTL (Flash Translation Layer).
In order to achieve the purpose of simulation disk, SSD use
FTL as middle-tier to receive block level requests (LSN, size)
of host file system and use FTL to produce a variety of control
commands. FTL includes three components: (1) Address
mapping, (2) Wear levelling, and (3) Garbage collection.
Common FTL mapping methods are: (1) page map (2)
block map, and (3) hybrid map [6, 7, 8, 9, 10]. Page map is the
most simple and direct way of mapping. When you power on
2015 IEEE 22nd International Conference on High Performance Computing
978-1-4673-8488-9/15 $31.00 © 2015 IEEE
DOI 10.1109/HiPC.2015.21
47