ST24C02: 2K EERAM for Microcontroller RAM Expansion

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"该资源是一份关于24C02的中文PDF文档，详细介绍了这款2K EERAM（Electrically Erasable Programmable Read-Only Memory）芯片，主要用于单片机RAM的扩展。24C02是I2C总线接口的串行EEPROM，具有2K（256x8位）存储容量。此外，文档还提到了24C02的不同版本，如03代表3K，04代表4K的变体。文档中涉及的芯片型号包括ST24C02R、ST24/25C02、ST24/25W02，以及它们的替代产品M24C02系列。" 24C02是一款由STMicroelectronics生产的串行EEPROM，适用于需要非易失性存储的嵌入式系统，特别是作为单片机的扩展RAM。它采用I2C（Inter-Integrated Circuit）总线通信协议，这是一种两线制接口，可以实现与微控制器的高效通信。芯片具有以下特点： 1. **存储容量**：2K位，即256字节（8位乘以256），分为不同的版本，如24C02提供2K的存储，而24C03和24C04分别提供3K和4K的存储。 2. **工作电压**：ST24x02系列的工作电压范围为3V到5.5V，ST25x02系列为2.5V到5.5V，而ST24C02R版本则支持1.8V到5.5V，更适合低电压应用。 3. **耐久性**：24C02芯片能承受1百万次的擦写周期，并保证40年的数据保留时间，确保了数据的长期可靠性。 4. **写入控制**：ST24W02和ST25W02版本具有硬件写入控制功能，增强了系统的安全性和稳定性。 5. **I2C兼容**：完全兼容I2C总线标准，支持字节和多字节写入（最多4字节）、页写入（最多8字节）以及随机和顺序读取模式。 6. **编程操作**：自定时编程周期使得编程过程无需外部时钟，自动地址递增功能简化了连续存储操作。 7. **ESD/LATCH-UP性能**：增强的ESD（Electrostatic Discharge）防护和LATCH-UP性能，提高了芯片在恶劣环境下的抗干扰能力。 8. **替代产品**：文档提到ST24C/W02系列被M24C02取代，ST25C/W02被M24C02-W取代，而ST24C02R则被M24C02-R替换，这些新产品可能提供了更先进的特性和改进。这份PDF文档对理解如何在项目中使用24C02芯片以及它的不同版本和替代产品非常有用，对于电子工程师尤其是从事嵌入式系统设计的人来说是宝贵的参考资料。通过阅读此文档，用户可以获得关于芯片的详细规格、操作模式以及如何集成到系统中的具体信息。

AI01100

BUS

SDA

MASTER

SCL

BUS

100 200 300 400

BUS

(pF)

max (kΩ)

= 5V

Figure 3. Maximum R

Value versus Bus Capacitance (C

BUS

) for an I

C Bus

The devices with this Write Control feature no

longer support the Multibyte Write mode of opera-

tion, however all other write modes are fully sup-

ported.

Refer to the AN404 Application Note for more de-

tailed information about Write Control feature.

DEVICE OPERATION

C Bus Background

The ST24/25x02 support the I

C protocol. This

protocol defines any device that sends data onto

the bus as a transmitter and any device that reads

the data as a receiver. The device that controls the

data transfer is known as the master and the other

as the slave. The master will always initiate a data

transfer and will provide the serial clock for syn-

chronisation. The ST24/25x02 are always slave

devices in all communications.

Start Condition. START is identified by a high to

low transition of the SDA line while the clock SCL

is stable in the high state. A START condition must

precede any command for data transfer. Except

during a programming cycle, the ST24/25x02 con-

tinuously monitor the SDA and SCL signals for a

START condition and will not respond unless one

is given.

Stop Condition. STOP is identified by a low to high

transition of the SDA line while the clock SCL is

stable in the high state. A STOP condition termi-

nates communication between the ST24/25x02

and the bus master. A STOP condition at the end

of a Read command, after and only after a No

Acknowledge, forces the standby state. A STOP

condition at the end of a Write command triggers

the internal EEPROM write cycle.

Acknowledge Bit (ACK). An acknowledge signal

is used to indicate a successfull data transfer. The

bus transmitter, either master or slave, will release

the SDA bus after sending 8 bits of data. During the

9th clock pulse period the receiver pulls the SDA

bus low to acknowledge the receipt of the 8 bits of

data.

Data Input. During data input the ST24/25x02

sample the SDA bus signal on the rising edge of

the clock SCL. Note that for correct device opera-

tion the SDA signal must be stable during the clock

low to high transition and the data must change

ONLY when the SCL line is low.

Memory Addressing. To start communication be-

tween the bus master and the slave ST24/25x02,

the master must initiate a START condition. Follow-

ing this, the master sends onto the SDA bus line 8

bits (MSB first) corresponding to the device select

code (7 bits) and a READ or WRITE bit.

SIGNAL DESCRIPTIONS (cont’d)

4/16

ST24/25C02, ST24C02R, ST24/25W02

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