TI TMS320F28068 Product Folder Sample

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The TI TMS320F28068 is a high-performance microcontroller specifically designed for real-time control applications. With its 32-bit architecture and powerful Delfino CPU core, this microcontroller is capable of executing complex control algorithms with ease. The device also features integrated analog and digital peripherals, making it a versatile solution for a wide range of applications. One of the key features of the TI TMS320F28068 is its high level of integration. The microcontroller includes a variety of communication interfaces such as SPI, I2C, UART, and CAN, allowing for seamless connectivity with external devices. Additionally, the device features multiple high-resolution PWM modules, making it ideal for motor control applications. In terms of processing power, the TI TMS320F28068 is equipped with a 32-bit floating-point Delfino CPU core, which enables fast and efficient execution of control algorithms. The device also features a comprehensive set of development tools, including the Code Composer Studio IDE and the MotorWare software suite, making it easy to get started with programming and development. Overall, the TI TMS320F28068 is a highly capable microcontroller that is ideal for a wide range of real-time control applications. Its combination of powerful processing capabilities, integrated peripherals, and comprehensive development tools make it a standout choice for engineers looking to develop advanced control systems. With its high level of integration and robust feature set, the TI TMS320F28068 is sure to meet the needs of even the most demanding control applications.

TMS320F28069

TMS320F28068

TMS320F28067

TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

ZHCS009F –NOVEMBER 2010 –REVISED MARCH 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

TMS320F28064 TMS320F28063 TMS320F28062

Table 4-1. Signal Descriptions

(1)

(continued)

PIN NAME

PIN NO.

I/O/Z DESCRIPTION

PZP

PFP

GPIO22

98 78

I/O/Z General-purpose input/output 22

EQEP1S I/O Enhanced QEP1 strobe

MCLKXA I/O McBSP transmit clock

SCITXDB O SCI-B transmit data

GPIO23

2 1

I/O/Z General-purpose input/output 23

EQEP1I I/O Enhanced QEP1 index

MFSXA I/O McBSP transmit frame synch

SCIRXDB I SCI-B receive data

GPIO24

97 77

I/O/Z General-purpose input/output 24

ECAP1 I/O Enhanced Capture input/output 1

EQEP2A

Enhanced QEP2 input A.

NOTE: eQEP2 is only available in the PZ and PZP packages.

SPISIMOB I/O SPI-B slave in, master out

GPIO25

39 31

I/O/Z General-purpose input/output 25

ECAP2 I/O Enhanced Capture input/output 2

EQEP2B I

Enhanced QEP2 input B.

NOTE: eQEP2 is only available in the PZ and PZP packages.

SPISOMIB I/O SPI-B slave out, master in

GPIO26

78 62

I/O/Z General-purpose input/output 26

ECAP3 I/O Enhanced Capture input/output 3

EQEP2I I/O

Enhanced QEP2 index.

NOTE: eQEP2 is only available in the PZ and PZP packages.

SPICLKB I/O SPI-B clock input/output

USB0DP

(3)

I/O

Positive Differential half of USB signal. To enable USB functionality on this pin, set the

USBIOEN bit in the GPACTRL2 register.

GPIO27

77 61

I/O/Z General-purpose input/output 27

HRCAP2 I High-Resolution Input Capture 2

EQEP2S I/O

Enhanced QEP2 strobe.

NOTE: eQEP2 is only available in the PZ and PZP packages.

SPISTEB I/O SPI-B slave transmit enable input/output

USB0DM

(3)

I/O

Negative Differential half of USB signal. To enable USB functionality on this pin, set the

USBIOEN bit in the GPACTRL2 register.

GPIO28

50 40

I/O/Z General-purpose input/output 28

SCIRXDA I SCI-A receive data

SDAA I/OD I

C data open-drain bidirectional port

TZ2 I Trip zone input 2

GPIO29

43 34

I/O/Z General-purpose input/output 29

SCITXDA O SCI-A transmit data

SCLA I/OD I

C clock open-drain bidirectional port

TZ3 I Trip zone input 3

GPIO30

41 33

I/O/Z General-purpose input/output 30

CANRXA I CAN receive

EQEP2I I/O

Enhanced QEP2 index.

NOTE: eQEP2 is only available in the PZ and PZP packages.

EPWM7A O Enhanced PWM7 Output A and HRPWM channel

TMS320F28069

TMS320F28068

TMS320F28067

TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

www.ti.com

ZHCS009F –NOVEMBER 2010–REVISED MARCH 2016

Submit Documentation Feedback

Product Folder Links: TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

TMS320F28064 TMS320F28063 TMS320F28062

Table 4-1. Signal Descriptions

(1)

(continued)

PIN NAME

PIN NO.

I/O/Z DESCRIPTION

PZP

PFP

GPIO31

40 32

I/O/Z General-purpose input/output 31

CANTXA O CAN transmit

EQEP2S I/O

Enhanced QEP2 strobe.

NOTE: eQEP2 is only available in the PZ and PZP packages.

EPWM8A O Enhanced PWM8 Output A and HRPWM channel

GPIO32

99 79

I/O/Z General-purpose input/output 32

SDAA I/OD I

C data open-drain bidirectional port

EPWMSYNCI I Enhanced PWM external sync pulse input

ADCSOCAO O ADC start-of-conversion A

GPIO33

100 80

I/O/Z General-purpose input/output 33

SCLA I/OD I

C clock open-drain bidirectional port

EPWMSYNCO O Enhanced PWM external synch pulse output

ADCSOCBO O ADC start-of-conversion B

GPIO34

68 55

I/O/Z General-purpose input/output 34

COMP2OUT O Direct output of Comparator 2

COMP3OUT O Direct output of Comparator 3

GPIO35

71 57

I/O/Z General-purpose input/output 35

TDI

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK.

GPIO36

72 58

I/O/Z General-purpose input/output 36

TMS

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked

into the TAP controller on the rising edge of TCK.

GPIO37

70 56

I/O/Z General-purpose input/output 37

TDO

O/Z

JTAG scan out, test data output (TDO). The contents of the selected register

(instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive).

GPIO38

67 54

I/O/Z General-purpose input/output 38

XCLKIN

External Oscillator Input. The path from this pin to the clock block is not gated by the

mux function of this pin. Care must be taken to not enable this path for clocking if it is

being used for the other functions.

TCK I JTAG test clock with internal pullup

GPIO39 66 53 I/O/Z General-purpose input/output 39

GPIO40

82 –

I/O/Z General-purpose input/output 40

EPWM7A O Enhanced PWM7 output A and HRPWM channel

SCITXDB O SCI-B transmit data

GPIO41

76 –

I/O/Z General-purpose input/output 41

EPWM7B O Enhanced PWM7 output B

SCIRXDB I SCI-B receive data

GPIO42

1 –

I/O/Z General-purpose input/output 42

EPWM8A O Enhanced PWM8 output A and HRPWM channel

TZ1 I Trip zone input 1

COMP1OUT O Direct output of Comparator 1

GPIO43

8 –

I/O/Z General-purpose input/output 43

EPWM8B O Enhanced PWM8 output B

TZ2 I Trip zone input 2

COMP2OUT O Direct output of Comparator 2

TMS320F28069

TMS320F28068

TMS320F28067

TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

ZHCS009F –NOVEMBER 2010 –REVISED MARCH 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

TMS320F28064 TMS320F28063 TMS320F28062

Table 4-1. Signal Descriptions

(1)

(continued)

PIN NAME

PIN NO.

I/O/Z DESCRIPTION

PZP

PFP

GPIO44

56 –

I/O/Z General-purpose input/output 44

MFSRA I/O McBSP receive frame synch

SCIRXDB I SCI-B receive data

EPWM7B O Enhanced PWM7 output B

GPIO50

42 –

I/O/Z General-purpose input/output 50

EQEP1A I Enhanced QEP1 input A

MDXA O McBSP transmit serial data

TZ1 I Trip zone input 1

GPIO51

48 –

I/O/Z General-purpose input/output 51

EQEP1B I Enhanced QEP1 input B

MDRA I McBSP receive serial data

TZ2 I Trip zone input 2

GPIO52

53 –

I/O/Z General-purpose input/output 52

EQEP1S I/O Enhanced QEP1 strobe

MCLKXA I/O McBSP transmit clock

TZ3 I Trip zone input 3

GPIO53

65 –

I/O/Z General-purpose input/output 53

EQEP1I I/O Enhanced QEP1 index

MFSXA I/O McBSP transmit frame synch

GPIO54

69 –

I/O/Z General-purpose input/output 54

SPISIMOA I/O SPI-A slave in, master out

EQEP2A I Enhanced QEP2 input A

HRCAP1 I High-Resolution Input Capture 1

GPIO55

75 –

I/O/Z General-purpose input/output 55

SPISOMIA I/O SPI-A slave out, master in

EQEP2B I Enhanced QEP2 input B

HRCAP2 I High-Resolution Input Capture 2

GPIO56

85 –

I/O/Z General-purpose input/output 56

SPICLKA I/O SPI-A clock input/output

EQEP2I I/O Enhanced QEP2 index

HRCAP3 I High-Resolution Input Capture 3

GPIO57

89 –

I/O/Z General-purpose input/output 57

SPISTEA I/O SPI-A slave transmit enable input/output

EQEP2S I/O Enhanced QEP2 strobe

HRCAP4 I High-Resolution Input Capture 4

GPIO58

94 –

I/O/Z General-purpose input/output 58

MCLKRA I/O McBSP receive clock

SCITXDB O SCI-B transmit data

EPWM7A O Enhanced PWM7 output A and HRPWM channel

(1) I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown

(2) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions.

For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the

GPIO block and the path to the JTAG block from a pin is enabled or disabled based on the condition of the TRST signal. See the

Systems Control and Interrupts chapter of the TMS320x2806x Piccolo Technical Reference Manual (SPRUH18).

(3) Depending on your USB application, additional pins may be required to maintain compliance with the USB 2.0 Specification. For more

information, see the Universal Serial Bus (USB) Controller chapter of the TMS320x2806x Piccolo Technical Reference Manual

(SPRUH18).

TMS320F28069

TMS320F28068

TMS320F28067

TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

www.ti.com

ZHCS009F –NOVEMBER 2010–REVISED MARCH 2016

Submit Documentation Feedback

Product Folder Links: TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

TMS320F28064 TMS320F28063 TMS320F28062

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Section 5.4 is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to V

, unless otherwise noted.

(3) Continuous clamp current per pin is ±2 mA.

(4) Long-term high-temperature storage or extended use at maximum temperature conditions may result in a reduction of overall device life.

For additional information, see the IC Package Thermal Metrics Application Report (SPRA953).

5 Specifications

5.1 Absolute Maximum Ratings

(1)(2)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Supply voltage

DDIO

(I/O and Flash) with respect to V

–0.3 4.6

with respect to V

–0.3 2.5

Analog voltage V

DDA

with respect to V

SSA

–0.3 4.6 V

Input voltage

(3.3 V) –0.3 4.6

(X1) –0.3 2.5

Output voltage V

–0.3 4.6 V

Input clamp current I

< 0 or V

> V

DDIO

)

(3)

–20 20 mA

Output clamp current I

< 0 or V

> V

DDIO

) –20 20 mA

Junction temperature

(4)

–40 150 °C

Storage temperature

(4)

stg

–65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.2 ESD Ratings for TMS320F2806xU

VALUE UNIT

(ESD)

Electrostatic discharge (ESD)

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)

±2000

Charged-device model (CDM), per JEDEC specification JESD22-

C101

(2)

±500

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 ESD Ratings for TMS320F2806x, TMS320F2806xM, and TMS320F2806xF

VALUE UNIT

TMS320F2806x, TMS320F2806xM, and TMS320F2806xF in 100-pin PZ and PZP packages

(ESD)

Electrostatic discharge

Human body model (HBM), per

AEC Q100-002

(1)

All pins ±2000

Charged device model (CDM),

per AEC Q100-011

All pins ±500

Corner pins on 100-pin PZ and

PZP:

1, 25, 26, 50, 51, 75, 76, 100

±750

TMS320F2806x, TMS320F2806xM, and TMS320F2806xF in 80-pin PN and PFP packages

(ESD)

Electrostatic discharge

Human body model (HBM), per

AEC Q100-002

(1)

All pins ±2000

Charged device model (CDM),

per AEC Q100-011

All pins ±500

Corner pins on 80-pin PN and

PFP:

1, 20, 21, 40, 41, 60, 61, 80

±750

TMS320F28069

TMS320F28068

TMS320F28067

TMS320F28066

TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062

ZHCS009F –NOVEMBER 2010 –REVISED MARCH 2016

www.ti.com

Submit Documentation Feedback

Product Folder Links: TMS320F28069 TMS320F28068 TMS320F28067 TMS320F28066 TMS320F28065

TMS320F28064 TMS320F28063 TMS320F28062

(1) Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37.

(2) The "Q" temperature option is not available on the 2806xU devices.

5.4 Recommended Operating Conditions

MIN NOM MAX UNIT

Device supply voltage, I/O, V

DDIO

2.97 3.3 3.63 V

Device supply voltage CPU, V

(When internal VREG is

disabled and 1.8 V is supplied externally)

1.71 1.8 1.995

Supply ground, V

0 V

Analog supply voltage, V

DDA

2.97 3.3 3.63 V

Analog ground, V

SSA

0 V

Device clock frequency (system clock) 2 90 MHz

High-level input voltage, V

(3.3 V) 2 V

DDIO

+ 0.3 V

Low-level input voltage, V

(3.3 V) V

– 0.3 0.8 V

High-level output source current, V

= V

OH(MIN)

, I

All GPIO/AIO pins –4

Group 2

(1)

–8

Low-level output sink current, V

= V

OL(MAX)

, I

All GPIO/AIO pins 4

Group 2

(1)

Junction temperature, T

T version –40 105

°C

S version –40 125

Ambient temperature, T

Q version

(2)

(Q100 qualification)

–40 125

°C

(1) When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage

) go out of range.

5.5 Electrical Characteristics

(1)

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-level output voltage

= I

MAX 2.4

= 50 μA V

DDIO

– 0.2

Low-level output voltage I

= I

MAX 0.4 V

Input current

(low level)

Pin with pullup

enabled

DDIO

= 3.3 V, V

= 0 V

All GPIO –80 –140 –205

μA

XRS pin –230 –300 –375

Pin with pulldown

enabled

DDIO

= 3.3 V, V

= 0 V ±2

Input current

(high level)

Pin with pullup

enabled

DDIO

= 3.3 V, V

= V

DDIO

±2

μA

Pin with pulldown

enabled

DDIO

= 3.3 V, V

= V

DDIO

28 50 80

Output current, pullup or

pulldown disabled

= V

DDIO

or 0 V ±2 μA

Input capacitance 2 pF

DDIO

BOR trip point Falling V

DDIO

2.50 2.78 2.96 V

DDIO

BOR hysteresis 35 mV

Supervisor reset release delay

time

Time after BOR/POR/OVR event is removed to XRS

release

400 800 μs

VREG V

output Internal VREG on 1.9 V

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