P82B96：I2C兼容双向总线缓冲器

需积分: 0 35 浏览量更新于2024-06-27 5 收藏 1.55MB PDF 举报

"TI-P82B96.pdf 是一份关于 I2C 兼容的双双向总线缓冲器 P82B96 的技术文档，该器件主要用于在不同电压和电流等级的总线配置之间实现双向数据传输，支持更长的电缆和更多的设备连接，同时隔离总线电容，防止对其他 I2C 总线或节点造成影响。" TI 的 P82B96 是一款专为扩展 I2C 总线功能而设计的缓冲器，其主要特点包括： 1. **操作电源电压范围**：P82B96 支持从 2V 到 15V 的宽电压范围，这使得它能够在多种不同的电源环境下工作，适应各种逻辑电平差异的系统。 2. **不同逻辑级别之间的接口**：这款器件能够连接运行在 2V 至 15V 不同电压级别的 I2C 总线，允许在不兼容的电压环境中进行通信。 3. **支持更长电缆和更多设备**：P82B96 允许主侧（Sx/Sy）的总线电容达到 400pF，传输侧（Tx/Ty）的总线电容可达 4000pF，这意味着它可以处理更长的电缆和更多连接到 I2C 总线的设备，而不影响系统的性能。 4. **隔离总线电容**：P82B96 可以隔离总线电容，使得新总线或远程 I2C 节点的负载不会对其他 I2C 总线造成影响，从而避免了总线负载过重导致的问题。 5. **高电流灌输出**：传输侧的输出（Tx/Ty）具有高电流灌能力，这确保了即使在驱动大电容负载时也能保持信号的稳定性。 6. **应用广泛**：这款缓冲器适用于需要长电缆连接、多设备通信或需要电气隔离的场合，如智能家居、工业自动化和嵌入式系统等。此外，文档还可能包含了 P82B96 的详细引脚配置、电气特性、工作模式、应用电路示例以及使用注意事项等内容，有助于开发者正确设计和使用该缓冲器以优化 I2C 系统的性能。用户可以通过提供的链接访问产品样本、购买信息、技术文档、工具软件以及技术支持和社区资源，获取更全面的信息。

P82B96

www.ti.com

SCPS144C –MAY 2006–REVISED MAY 2015

7.6 Electrical Characteristics: V

= 3 V to 3.6 V

= 3 V to 3.6 V, voltages are specified with respect to GND (unless otherwise noted)

= 25°C T

= – 40° C to 85°C

PARAMETER TEST CONDITIONS UNIT

MIN TYP

(1)

MAX MIN MAX

Temperature

ΔV/ΔT

coefficient of Sx, Sy –2 mV/°C

input thresholds

, I

= 3 mA 0.8 0.88 1 See

(2)

Low-level output

Sx, Sy V

voltage

, I

= 0.2 mA 0.67 0.73 0.79 See

(2)

Temperature

coefficient of

ΔV/ΔT

OUT

Sx, Sy I

, I

= 0.2 mA –1.8 mV/°C

output low

levels

(3)

Quiescent supply current Sx = Sy = V

0.9 1.8 2 mA

Additional supply

ΔI

current per pin Tx, Ty 1.7 2.75 3 mA

low

Dynamic output

sink capability V

, V

> 2 V, V

, V

= low 7 18 5.7 mA

on I

C bus

IOS

Sx, Sy

Leakage current V

, V

= 5 V,

0.1 1 1 μA

on I

C bus V

, V

= high

Dynamic output V

, V

> 1 V,

sink capability V

, V

= low on I

C bus = 60 100 60 mA

on buffered bus 0.4 V

IOT

Tx, Ty

Leakage current V

, V

= V

= 3.3 V,

0.1 1 1 μA

on buffered bus V

, V

= high

Input current

Sx, Sy Bus low, V

, V

= high –1 1

from I

C bus

Input current

Bus low, V

, V

= 0.4 V –1 1

from buffered bus μA

Rx, Ry

Leakage current

on buffered bus V

, V

= V

1 1.5

input

Input logic-level high

0.65 0.7 See

(2)

threshold

(4)

on normal I

C bus

Sx, Sy

Input logic-level low

0.6 0.65 See

(2)

threshold

(4)

on normal I

C bus

Input threshold 0.58 x V

Input logic level high 0.58 x V

Rx, Ry Input threshold 0.5 x V

0.42 x 0.42 x

Input logic level low

output low at 3 mA) –

Input/output logic

IOdiff

Sx, Sy (V

input high max) for I

C 100 150 100 mV

level difference

(5)

applications

voltage at Sx, Sy are low, V

ramping,

Sx, Sy

IOrel

which all buses voltage on Tx, Ty lowered until 1 1 V

Tx, Ty

are released released

Temperature coefficient of

ΔV/ΔT

REL

–4 mV/°C

release voltage

Input capacitance Rx, Ry 2.5 4 4 pF

(1) Typical value is at V

= 3.3 V, T

= 25°C

(2) See the Typical Characteristics section of this data sheet.

(3) The output logic low depends on the sink current.

(4) The input logic threshold is independent of the supply voltage.

(5) The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for V

output low always exceeds the

minimum V

input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.

While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another

P82B96, this has no consequences for normal applications.

Product Folder Links: P82B96

P82B96

SCPS144C –MAY 2006 –REVISED MAY 2015

www.ti.com

7.7 Electrical Characteristics: V

= 4.5 V to 5.5 V

= 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted)

= 25°C T

= – 40° C to 85°C

PARAMETER TEST CONDITIONS UNIT

MIN TYP

(1)

MAX MIN MAX

Temperature

ΔV/ΔT

coefficient of input Sx, Sy –2 mV/°C

thresholds

, I

= 3 mA 0.8 0.88 1 See

(2)

Low-level output

Sx, Sy V

voltage

, I

= 0.2 mA 0.67 0.73 0.79 See

(2)

Temperature

coefficient of

ΔV/ΔT

OUT

Sx, Sy I

, I

= 0.2 mA –1.8 mV/°C

output low

levels

(3)

Quiescent supply current Sx = Sy = V

0.9 1.8 2 mA

Additional supply

ΔI

current Tx, Ty 1.7 2.75 3 mA

per pin low

Dynamic output

, V

> 2 V,

sink capability 7 18 6 mA

, V

= low

on I

C bus

IOS

Sx, Sy

Leakage current V

, V

= 5 V,

0.1 1 1 μA

on I

C bus V

, V

= high

Dynamic output V

, V

> 1 V,

sink capability V

, V

= low on I

C bus = 60 100 60 mA

on buffered bus 0.4 V

IOT

Tx, Ty

Leakage current V

, V

= V

= 5 V,

0.1 1 1 μA

on buffered bus V

, V

= high

Input current

Sx, Sy Bus low, V

, V

= high –1 1

from I

C bus

Input current

Bus low, V

, V

= 0.4 V –1 1

from buffered bus μA

Rx, Ry

Leakage current

on buffered bus V

, V

= V

1 1.5

input

Input logic-level high

threshold

(4)

0.65 0.7 See

(2)

on normal I

C bus

Sx, Sy

Input logic-level low

threshold

(4)

0.6 0.65 See

(2)

on normal I

C bus

Input threshold V

0.58 x

Input logic level high 0.58 x V

Rx, Ry Input threshold 0.5 x V

0.42 x 0.42 x

Input logic level low

output low at 3 mA) –

Input/output logic

IOdiff

Sx, Sy (V

input high max) for I

C 100 150 100 mV

level difference

(5)

applications

voltage at Sx, Sy are low, V

Sx, Sy

IOrel

which all buses ramping, voltage on Tx, Ty 1 1 V

Tx, Ty

are released lowered until released

(1) Typical value is at V

= 5 V, T

= 25°C

(2) See the Typical Characteristics section of this data sheet.

(3) The output logic low depends on the sink current.

(4) The input logic threshold is independent of the supply voltage.

(5) The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for V

output low always exceeds the

minimum V

input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.

While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another

P82B96, this has no consequences for normal applications.

Product Folder Links: P82B96

剩余35页未读，继续阅读

不觉明了

粉丝: 3509
资源: 5759

P82B96：I2C兼容双向总线缓冲器

TI-P82B715.pdf

"TI-P82B715.pdf: I2C缓冲器使用说明

postgresql-server-13.3-1.module_el8.5.0+843+2fa7d82b.aarch64.rpm

postgresql-test-13.3-1.module_el8.5.0+843+2fa7d82b.aarch64.rpm

postgresql-docs-13.3-1.module_el8.5.0+843+2fa7d82b.aarch64.rpm

postgresql-plperl-13.3-1.module_el8.5.0+843+2fa7d82b.aarch64.rpm

postgresql-pltcl-13.3-1.module_el8.5.0+843+2fa7d82b.aarch64.rpm

pgaudit-1.5.0-1.module_el8.5.0+843+2fa7d82b.aarch64.rpm

postgresql-13.3-1.module_el8.5.0+843+2fa7d82b.aarch64.rpm

postgresql-plperl-13.3-1.module_el8.5.0+843+2fa7d82b.ppc64le.rpm

最新资源