NXP FXOS8700CQ：六轴传感器，低功耗，I2C/SPI接口，-40°C至+85°C工作范围

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FXOS8700CQ是一款由NXP公司推出的高性能六轴传感器，集成了线性加速度计和磁强计功能。这款小巧且低功耗的器件采用QFN-16封装，提供了紧凑的解决方案，适用于对空间和功耗有严格要求的应用场景。其主要特性包括： 1. 多轴感应能力：FXOS8700CQ作为一款六轴传感器，它包含一个3轴加速度计和一个3轴磁强计，能够同时测量设备在三个维度上的加速度变化和磁场强度，这对于姿态感知、导航系统以及运动跟踪等领域极为有用。 2. 电压兼容性：该设备支持宽范围的供电电压，包括1.95V到3.6V的电源电压（VDD）和1.62V到3.6V的输入/输出电压（VDDio），这使得它能够在多种电源条件下稳定工作，增强了设备的灵活性和适应性。 3. 动态范围选择：加速度计部分具有±2g、±4g和±8g三种动态可调的满量程范围，允许用户根据应用需求精确地设置敏感度。磁强计的满量程固定在±1200μT，提供稳定的磁感应测量。 4. 可定制的数据输出速率：FXOS8700CQ允许用户选择传感器的输出数据速率（ODR），从1.563Hz到800Hz，如果以混合模式运行，即两个传感器同时激活时，最高可达400Hz的速率，这保证了数据传输的实时性和准确性。 5. 温度适应性：该传感器设计用于扩展的工作温度范围，从-40°C到+85°C，确保在各种环境条件下都能保持良好的性能。 6. 智能嵌入式功能：FXOS8700CQ内置了智能功能，简化了系统设计，提高了能效，减少了外部组件的需求，从而降低了整体成本。这些特点使得FXOS8700CQ成为工业级物联网、智能手机、可穿戴设备以及游戏手柄等应用的理想选择，其高度集成和高效性使其在紧凑型设计中实现精确的运动和磁场检测。

Product data sheet Rev. 7.0 — 22 March 2016 16 of 113

NXP Semiconductors

FXOS8700CQ

6-axis sensor with integrated linear accelerometer and magnetometer

Fig 6. I

C timing diagram

10.2 SPI interface characteristics

SPI interface is a classical master/slave serial port. The FXOS8700CQ is always

considered as the slave and thus is never initiating the communication.

Table 12

and Figure 7 describe the timing requirements for the SPI system.

< Single-byte read >

Master

ST Device address[6:0] W Register address[7:0] SR Device address[6:0] R NAK SP

Slave

AK AK AK Data[7:0]

< Multiple-byte read >

Master

ST Device address[6:0] W Register address[7:0] SR Device address[6:0] R AK

Slave

AK AK AK Data[7:0]

Master

AK AK NAK SP

Slave

Data[7:0] Data[7:0] Data[7:0]

< Multiple-byte write >

Master

ST Device address[6:0] W Register address[7:0] Data[7:0] Data[7:0] SP

Slave

AK AK AK AK

< Single-byte write >

Master

ST Device address[6:0] W Register address[7:0] Data[7:0] SP

Slave

AK AK AK

Legend

ST: Start condition SP: Stop condition NAK: No acknowledge W: Write = 0

SR: Repeated start condition AK: Acknowledge R: Read = 1

Table 12. SPI timing

Function Symbol Min Max Unit

Operating frequency Of -1 MHz

SCLK period tSCLK 1000 - ns

SCLK high time tCLKH 500 - ns

SCLK low time tCLKL 500 - ns

CS_B lead time tSCS 65 - ns

CS_B lag time tHCS 65 - ns

MOSI data setup time tSET 25 - ns

Product data sheet Rev. 7.0 — 22 March 2016 18 of 113

NXP Semiconductors

FXOS8700CQ

6-axis sensor with integrated linear accelerometer and magnetometer

The FXOS8700CQ SPI configuration is as follows:

• Polarity: rising/falling

• Phase: sample/setup

• Order: MSB first

Data is sampled during the rising edge of SCLK and set up during the falling edge of

SCLK.

10.2.2 SPI read/write operations

A read operation is initiated by transmitting a 0 for the R/W bit. Then the 8-bit register

address, ADDR[7:0] is encoded in the first and second serialized bytes. Subsequent bits

are ignored by the part. The read data is deserialized from the MISO pin.

Similarly a write operation is initiated by transmitting a 1 for the R/W bit. After the first and

second serialized bytes multiple-data bytes can be transmitted into consecutive registers,

starting from the indicated register address in ADDR[7:0].

An SPI transaction is started by asserting the CS_B pin (high-to-low transition), and

ended by deasserting the CS_B pin (low-to-high transition).

The registers embedded inside FXOS8700CQ are accessed through either an I

C, or a

SPI serial interface. To enable either interface the VDDIO line must be connected to the

interface supply voltage. If VDD is not present and VDDIO is present FXOS8700CQ is in

shutdown mode and communications on the interface are ignored. If VDDIO is held high,

VDD can be powered off and the communications pins will be in a high impedance state.

This will allow communications to continue on the bus with other devices.

(1) Data bytes must be transmitted to the slave (FXOS8700CQ) using the MOSI pin by the master when R/W = 1. Data bytes will

be transmitted by the slave (FXOS8700CQ) to the master using the MISO pin when R/W = 0. The first two bytes are always

transmitted by the master using the MOSI pin. That is, a transaction is always initiated by master.

Fig 8. SPI single-burst read/write transaction diagram

Table 13. Serial interface pin descriptions

Pin name Pin description

VDDIO Digital interface power

SA1/CS_B I

C second least significant bit of device address/SPI chip select

SCL/SCLK I

C/SPI serial clock

SDA/MOSI I

C serial data/SPI master serial data out slave serial data in

SA0/MISO I

C least significant bit of the device address/SPI master serial data in slave out

Product data sheet Rev. 7.0 — 22 March 2016 19 of 113

NXP Semiconductors

FXOS8700CQ

6-axis sensor with integrated linear accelerometer and magnetometer

10.2.3 I

C/SPI auto detection

FXOS8700CQ employs an interface mode, auto-detection circuit that will select either I

or SPI interface mode based on the state of the SA0 pin during power up or when exiting

reset. Once set for I

C or SPI operation, the device will remain in I

C or SPI mode until the

device is reset or powered down and the auto-detection process is repeated. Please note

that when SPI interface mode is desired, care must be taken to ensure that no other slave

device drives the common SA0/MISO pin during the 1 ms period after a hard or soft reset

or powerup event.

10.2.4 Power supply sequencing and I

C/SPI mode auto-detection

FXOS8700CQ does not have any specific power supply sequencing requirements

between VDD and VDDIO voltage supplies to ensure normal operation. To ensure correct

operation of the I

C/SPI auto-detection function, VDDIO should be applied before or at the

same time as VDD. If this order cannot be maintained, the user should either toggle the

RST line or power cycle the VDD rail in order to force the auto-detect function to restart

and correctly identify the desired interface. FXOS8700CQ will indicate completion of the

reset sequence by toggling the INT1 pin from logic high to low to high over a 500 ns

period. If the INT1 pin was already low prior to the reset event, it will only go high.

11. Modes of operation

Table 14. I

C/SPI auto detection

SA0 Slave address

GND I

VDDIO I

Floating SPI

Fig 9. FXOS8700CQ power mode transition diagram

Table 15. Mode of operation description

Mode I

C/SPI bus state VDD VDDIO Function description

OFF Powered down <1.8 V VDDIO can be > VDD The device is powered off. All analog and digital

blocks are shutdown. I

C bus inhibited.

Standby I

C/SPI communication

with FXOS8700CQ is

possible

ON VDDIO = High

VDD = High

Active bit is cleared

Only digital blocks are enabled.

Analog subsystem is disabled. Internal clocks

disabled.

Active

(wake/sleep)

C/SPI communication

with FXOS8700CQ is

possible

ON VDDIO = High

VDD = High

Active bit is set

All blocks are enabled (digital and analog).

Product data sheet Rev. 7.0 — 22 March 2016 20 of 113

NXP Semiconductors

FXOS8700CQ

6-axis sensor with integrated linear accelerometer and magnetometer

All register contents are preserved when transitioning from active-to-standby mode, but

some registers are reset when transitioning from standby-to-active. These registers are

noted in Table16

. The sleep and wake modes are active modes. For more information on

how to use the sleep and wake modes and configuring the device to transition between

them, please refer to Section 12

or NXP application note AN4074.

12. Embedded functionality

FXOS8700CQ is a low-power, digital output, 6-axis sensor with both I

C and SPI

interfaces. Extensive embedded functionality is provided to detect inertial and magnetic

events at low power, with the ability to notify the host processor of an event using either of

the two programmable interrupt pins. The embedded functionality includes:

• 8-bit or 14-bit accelerometer data which includes high-pass filtered data, and 8-bit or

16-bit magnetometer data

• Four different oversampling options for the accelerometer output data, and eight for

the magnetometer. The oversampling settings allow the end user to optimize the

resolution versus power trade-off in a given application.

• A low-noise accelerometer mode that functions independently of the oversampling

modes for even higher resolution

• Low-power, auto-wake/sleep function for conserving power in portable battery

powered applications

• Accelerometer pulse-detection circuit which can be used to detect directional single

and double taps

• Accelerometer directional motion- and freefall-event detection with programmable

threshold and debounce time

• Acceleration transient detection with programmable threshold and debounce time.

Transient detection can employ either a high-pass filter or use the difference between

reference and current sample values.

• Orientation detection with programmable hysteresis for smooth transitions between

portrait/landscape orientations

• Accelerometer vector-magnitude change event detection with programmable

reference, threshold, and debounce time values

• Magnetic threshold event detection with programmable reference, threshold, and

debounce time

• Magnetometer vector-magnitude change event detection with programmable

reference, threshold and debounce time values

• Magnetic min/max detection circuit which can also be used for autonomous

calibration of magnetic hard-iron offset

Many different configurations of the above functions are possible to suit the needs of the

end application. Separate application notes are available to further explain the different

configuration settings and potential use cases.

12.1 Factory calibration

FXOS8700CQ's integrated accelerometer and magnetometer sensors are factory

calibrated for sensitivity and offset on each axis. The trim values are stored in non-volatile

memory (NVM). On power-up, the trim parameters are read from NVM and applied to the

internal compensation circuitry. After mounting the device to the PCB, the user may

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