IMX6独步车规级多媒体处理器：集成与设计详解

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IMX6原理图是Freescale半导体提供的一份详细设计文档，针对其i.MX6SoloX系列处理器。该处理器是一款专为汽车信息娱乐和车载应用设计的高性能产品，旨在满足市场对多媒体集成、高功能性和低功耗的需求。核心配置上，i.MX6SoloX集成了先进的ARM Cortex-A9处理器，最高工作频率可达800MHz，以及ARM Cortex-M4处理器，支持200MHz的运行速度。这种异构多核架构使得系统能实现更高级别的集成度，同时具备智能的低功耗管理和快速实时响应能力。文档详细介绍了处理器的封装选项，包括塑料封装的三种规格：BGA19x19mm（0.8mm间距）、BGA17x17mm（0.8mm间距）和BGA14x14mm（0.65mm间距），便于不同的设计需求和板级集成。订购信息可在文档第3页的表1中找到。作为一款面向汽车行业和信息娱乐市场的处理器，i.MX6SoloX注重了功能的丰富性和系统效率，尤其在处理多媒体任务、HMI（人机交互界面）以及显示相关的车载信息娱乐系统时表现出色。此外，由于它兼顾高性能与节能，能够适应不断增长的对车辆智能化和用户体验提升的需求。这份IMX6SXAEC Rev.0，日期为2/2015的技术数据手册，不仅包含了硬件原理图，还涵盖了详细的技术规格、接口说明、引脚布局以及安全特性等关键信息。对于任何使用或设计基于i.MX6SoloX平台的项目来说，这份文档是不可或缺的参考资料，能帮助工程师们深入了解并优化他们的系统设计。

i.MX 6SoloX Automotive and Infotainment Applications Processors, Rev. 0

16 Freescale Semiconductor, Inc.

Modules List

3.1 Special Signal Considerations

Table 3 lists special signal considerations for the i.MX 6SoloX processors. The signal names are listed in

alphabetical order.

The package contact assignments can be found in Section 6, “Package Information and Contact

Assignments.” Signal descriptions are provided in the i.MX 6SoloX Applications Processor Reference

Manual (IMX6SXRM).

WDOG1

WDOG3

Watch Dog Timer Peripherals The Watch Dog Timer supports two comparison points

during each counting period. Each of the comparison

points is configurable to evoke an interrupt to the ARM

core, and a second point evokes an external event on the

WDOG line.

WDOG2

(TZ)

Watch Dog (TrustZone) Timer Peripherals The TrustZone Watchdog (TZ WDOG) timer module

protects against TrustZone starvation by providing a

method of escaping normal mode and forcing a switch to

the TZ mode. TZ starvation is a situation where the

normal OS prevents switching to the TZ mode. Such

situation is undesirable as it can compromise the

system’s security. Once the TZ WDOG module is

activated, it must be serviced by TZ software on a periodic

basis. If servicing does not take place, the timer times out.

Upon a time-out, the TZ WDOG asserts a TZ mapped

interrupt that forces switching to the TZ mode. If it is still

not served, the TZ WDOG asserts a security violation

signal to the CSU. The TZ WDOG module cannot be

programmed or deactivated by a normal mode software.

Table 3. Special Signal Considerations

Signal Name Remarks

CCM_CLK1_P/

CCM_CLK1_N

CCM_CLK2

Two general purpose differential high speed clock Input/outputs are provided.

Any or both of them could be used:

• To feed external reference clock to the PLLs and further to the modules inside SoC, for example

as alternate reference clock for PCIe, Video/Audio interfaces, etc.

• To output internal SoC clock to be used outside the SoC as either reference clock or as a

functional clock for peripherals

See the i.MX 6SoloX Applications Processor Reference Manual (IMX6SXRM) for details on the

respective clock trees.

The clock inputs/outputs are LVDS differential pairs compatible with TIA/EIA-644 standard, the

frequency range supported is 0...600 MHz.

Alternatively one may use single ended signal to drive CLKx_P input. In this case corresponding

CLKx_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.

Termination should be provided in case of high frequency signals.

See LVDS pad electrical specification for further details.

After initialization, the CLKx inputs/outputs could be disabled (if not used). If unused any or both of

the CLKx_N/P pairs may be left floating.

Table 2. i.MX 6SoloX Modules List (continued)

Block Mnemonic Block Name Subsystem Brief Description

Modules List

i.MX 6SoloX Automotive and Infotainment Applications Processors, Rev. 0

Freescale Semiconductor, Inc. 17

RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz

crystal, (≤100 kΩ ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.

Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal

load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to

account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but

relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO

to either power or ground (>100 MΩ). This will debias the amplifier and cause a reduction of startup

margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.

If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin should

be left floating or driven with a complimentary signal. The logic level of this forcing clock should not

exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical conditions.

In case when high accuracy real time clock are not required system may use internal low frequency

ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO floating.

XTALI/XTALO A 24.0 MHz crystal should be connected between XTALI and XTALO.

The crystal must be rated for a maximum drive level of 250 μW. An ESR (equivalent series

resistance) of typical 80 Ω is recommended. Freescale BSP (board support package) software

requires 24 MHz on XTALI/XTALO.

The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this

case, XTALI must be directly driven by the external oscillator and XTALO is floated.

If this clock is used as a reference for USB and PCIe, then there are strict frequency tolerance and

jitter requirements. See OSC24M chapter and relevant interface specifications chapters for details.

DRAM_VREF When using DDR_VREF with DDR I/O, the nominal reference voltage must be half of the

NVCC_DRAM supply. The user must tie DDR_VREF to a precision external resistor divider. Use a

1kΩ 0.5% resistor to GND and a 1 kΩ 0.5% resistor to NVCC_DRAM. Shunt the resistor from

DRAM_VREF to ground with a closely mounted 0.1 μF capacitor.

To reduce supply current, a pair of 1.5 kΩ 0.1% resistors can be used. Using resistors with

recommended tolerances ensures the ± 2% DDR_VREF tolerance (per the DDR3 specification) is

maintained when four DDR3 ICs plus the i.MX 6SoloX are drawing current on the resistor divider.

ZQPAD DRAM calibration resistor 240 Ω 1% used as reference during DRAM output buffer driver

calibration should be connected between this pad and GND.

NVCC_LVDS_2P5 The DDR pre-drivers share the NVCC_LVDS_2P5 ball with the LVDS interface. This ball can be

shorted to VDD_HIGH_CAP on the circuit board.

GPANAIO This signal is reserved for Freescale manufacturing use only. User must leave this connection

floating.

JTAG_nnnn The JTAG interface is summarized in Table 4. Use of external resistors is unnecessary. However,

if external resistors are used, the user must ensure that the on-chip pull-up/down configuration is

followed. For example, do not use an external pull down on an input that has on-chip pull-up.

JTAG_TDO is configured with a keeper circuit such that the floating condition is eliminated if an

external pull resistor is not present. An external pull resistor on JTAG_TDO is detrimental and

should be avoided.

JTAG_MOD is referenced as SJC_MOD in the i.MX 6SoloX Applications Processor Reference

Manual (IMX6SXRM). Both names refer to the same signal. JTAG_MOD must be externally

connected to GND for normal operation. Termination to GND through an external pull-down resistor

(such as 1 kΩ) is allowed. JTAG_MOD set to high configures the JTAG interface to mode compliant

with IEEE1149.1 standard. JTAG_MOD set to low configures the JTAG interface for common

software debug adding all the system TAPs to the chain.

NC These signals are No Connect (NC) and should be floated by the user.

Table 3. Special Signal Considerations (continued)

Signal Name Remarks

i.MX 6SoloX Automotive and Infotainment Applications Processors, Rev. 0

18 Freescale Semiconductor, Inc.

Modules List

3.2 Recommended Connections for Unused Analog Interfaces

Table 5 shows the recommended connections for unused analog interfaces.

POR_B This cold reset negative logic input resets all modules and logic in the IC.

May be used in addition to internally generated power on reset signal (logical AND, both internal

and external signals are considered active low).

ONOFF ONOFF can be configured in debounce, off to on time, and max timeout configurations. The

debounce and off to on time configurations supports 0, 50, 100 and 500 msecs. Debounce is used

to generate the power off interrupt. While in the ON state, if ONOFF button is pressed longer than

the debounce time, the power off interrupt is generated. Off to on time supports the time it takes to

request power on after a configured button press time has been reached. While in the OFF state,

if ONOFF button is pressed longer than the off to on time, the state will transition from OFF to ON.

Max timeout configuration supports 5, 10, 15 secs and disable. Max timeout configuration supports

the time it takes to request power down after ONOFF button has been pressed for the defined time.

TEST_MODE TEST_MODE is for Freescale factory use. The user must tie this pin directly to GND.

PCIE_REXT The impedance calibration process requires connection of reference resistor 200 Ω 1% precision

resistor on PCIE_REXT pad to ground.

Table 4. JTAG Controller Interface Summary

JTAG I/O Type On-chip Termination

JTAG_TCK Input 47 kΩ

pull-up

JTAG_TMS Input 47 kΩ pull-up

JTAG_TDI Input 47 kΩ pull-up

JTAG_TDO 3-state output Keeper

JTAG_TRSTB Input 47 kΩ pull-up

JTAG_MOD Input 100 kΩ pull-up

Table 5. Recommended Connections for Unused Analog Interfaces

Module Pad Name

Recommendations

if Unused

ADC ADC_VREFH VDDA_ADC_3P3

ADC_VREFL Ground

ADC1_IN0, ADC1_IN1, ADC1_IN2, ADC1_IN3,

ADC2_IN0, ADC2_IN1, ADC2_IN2, ADC2_IN3

Float

CCM CCM_CLK1_N, CCM_CLK1_P, CCM_CLK2 Float

LDB LVDS_CLK_N, LVDS_CLK_P, LVDS_DATA0_N, LVDS_DATA0_P, LVDS_DATA1_N,

LVDS_DATA1_P, LVDS_DATA2_N, LVDS_DATA2_P, LVDS_DATA3_N, LVDS_DATA3_P

Float

PCIe PCIE_REXT, PCIE_RX_N, PCIE_RX_P, PCIE_TX_N, PCIE_TX_P Float

PCIE_VP, PCIE_VPH, PCIE_VPTX Ground

Table 3. Special Signal Considerations (continued)

Signal Name Remarks

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