PCI 3.0标准详解：硬件开发者的必读文档

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PCI 3.0规范是针对硬件开发人员的重要参考文档，由PCI-SIG（Peripheral Component Interconnect Special Interest Group，外设组件互连标准兴趣组）发布，于2002年8月12日更新到第3.0版本。该标准详细定义了PCI接口的架构、物理尺寸、传输速率以及其他关键特性，旨在确保硬件工程师在设计和实现基于PCI的系统时能够遵循一致且高效的标准。 PCI Local Bus Specification, Revision 3.0涵盖了以下主要内容： 1. **历史修订** - PCI 1.0最初发布于1992年6月22日，后续版本（如2.0、2.1、2.2和3.0）分别在1993年4月30日、1995年6月1日、1998年12月18日和2002年8月12日进行更新，每次修订都增加了新的功能、澄清了细节，并对先前存在的问题进行了修正。 - 特别值得注意的是，3.0版本删除了对5.0伏特唯一键接系统板连接器的支持，这可能反映了技术演进和对兼容性需求的调整。 2. **接口定义** - 3.0规范提供了详尽的接口规格，包括数据线配置、地址线、控制信号线等的描述，这些都是构建现代计算机内部组件间高速通信的基础。 3. **传输速率** - PCI 3.0显著提升了数据传输速率，从早期版本的相对较低的速度提升到了更高的带宽，这对于支持高性能计算和多媒体应用至关重要。 4. **可靠性与责任声明** - PCI-SIG明确声明，该规范及其内容仅供参考，并不保证无误，也不承诺随时更新信息。用户需直接联系PCI-SIG获取最新版本，以确保设计和实施的准确性。 5. **联系信息** - 如有对规范的疑问或关于加入PCI-SIG的兴趣，可以联系PCI-SIG办公室，获取最新规格或了解会员服务。 PCI 3.0 specification是硬件工程师在设计PC主板、扩展卡和相关设备时不可或缺的参考资料，它奠定了现代计算机体系结构中的重要基础，对于理解计算机内部组件如何通过PCI接口高效协作有着核心价值。随着技术的不断进步，后续的规范修订可能会引入更多先进的功能和技术，但3.0版本仍为当前许多系统设计的基础。

PCI SPECIFICATIONS

VOLUME 1 16 PCI-SIG

PCI LOCAL BUS SPECIFICATION, REV. 3.0

1.3. PCI Local Bus Applications

The PCI Local Bus has been defined with the primary goal of establishing an industry

standard, high performance local bus architecture that offers low cost and allows

differentiation. While the primary focus is on enabling new price-performance points in

today's systems, it is important that a new standard also accommodates future system

requirements and be applicable across multiple platforms and architectures. Figure 1-1

shows the multiple dimensions of the PCI Local Bus.

Servers

Mobile

High End

Desktops

Low, Mid-

Range

Desktop

Auto

Configuration

64-bit Upgrade

Path

PCI 33

PCI 66

PCI-X 66

PCI-X 133

PCI-X 266

PCI-X 533

PCI Express

A-0151

Figure 1-1: PCI Local Bus Applications

While the initial focus of local bus applications was on low to high end desktop systems, the

PCI Local Bus also comprehends the requirements from mobile applications up through

servers. The PCI Local Bus specifies 3.3 volt signaling requirements.

The PCI component and add-in card interface is processor independent, enabling an

efficient transition to future processor generations and use with multiple processor

architectures. Processor independence allows the PCI Local Bus to be optimized for I/O

functions, enables concurrent operation of the local bus with the processor/memory

subsystem, and accommodates multiple high performance peripherals in addition to graphics

(motion video, LAN, SCSI, FDDI, hard disk drives, etc.). Movement to enhanced video

and multimedia displays (i.e., HDTV and 3D graphics) and other high bandwidth I/O will

continue to increase local bus bandwidth requirements. A transparent 64-bit extension of

the 32-bit data and address buses is defined, doubling the bus bandwidth and offering

forward and backward compatibility of 32-bit and 64-bit PCI Local Bus peripherals. A

forward and backward compatible PCI-X specification (see the PCI-X Addendum to the PCI

Local Bus Specification) is also defined, increasing the bandwidth capabilities of the 33 MHz

definition by a factor of four.

The PCI Local Bus standard offers additional benefits to the users of PCI based systems.

Configuration registers are specified for PCI components and add-in cards. A system with

embedded auto configuration software offers true ease-of-use for the system user by

automatically configuring PCI add-in cards at power on.

PCI SPECIFICATIONS

VOLUME 1 18 PCI-SIG

PCI LOCAL BUS SPECIFICATION, REV. 3.0

1.5. PCI Local Bus Features and Benefits

The PCI Local Bus was specified to establish a high performance local bus standard for

several generations of products. The PCI specification provides a selection of features that

can achieve multiple price-performance points and can enable functions that allow

differentiation at the system and component level. Features are categorized by benefit as

follows:

High Performance

 Transparent upgrade from 32-bit data path at 33 MHz

(132 MB/s peak) to 64-bit data path at 33 MHz

(264 MB/s peak), from 32-bit data path at 66 MHz (264 MB/s

peak) to 64-bit data path at 66 MHz (532 MB/s peak), and from

32-bit data path at 133 MHz (532 MB/s peak) to 64-bit data path

at 133 MHz (1064 MB/s peak).

 Variable length linear and cacheline wrap mode bursting for both

read and writes improves write dependent graphics performance.

 Low latency random accesses (60-ns write access latency for

33 MHz PCI to 30-ns for 133 MHz PCI-X to slave registers

from master parked on bus).

 Capable of full concurrency with processor/memory subsystem.

 Synchronous bus with operation up to 33 MHz, 66 MHz, or

133 MHz.

 Hidden (overlapped) central arbitration.

Low Cost

 Optimized for direct silicon (component) interconnection; i.e.,

no glue logic. Electrical/driver (i.e., total load) and frequency

specifications are met with standard ASIC technologies and

other typical processes.

 Multiplexed architecture reduces pin count (47 signals for target;

49 for master) and package size of PCI components or provides

for additional functions to be built into a particular package size.

Ease of Use

 Enables full auto configuration support of PCI Local Bus add-in

cards and components. PCI devices contain registers with the

device information required for configuration.

Longevity

 Processor independent. Supports multiple families of processors

as well as future generations of processors (by bridges or by

direct integration).

 Support for 64-bit addressing.

 The 3.3-volt system signaling environment is specified with the

universal add-in card providing backward compatibility to 5-volt

signaling systems.

PCI SPECIFICATIONS

VOLUME 1 20 PCI-SIG

PCI LOCAL BUS SPECIFICATION, REV. 3.0

1.6. Administration

This document is maintained by PCI-SIG. PCI-SIG, an incorporated non-profit

organization of members of the microcomputer industry, was established to monitor and

enhance the development of the PCI Local Bus in three ways. PCI-SIG is chartered to:

 Maintain the forward compatibility of all PCI Local Bus revisions or addenda.

 Maintain the PCI Local Bus specification as a simple, easy to implement, stable

technology in the spirit of its design.

 Contribute to the establishment of the PCI Local Bus as an industry wide standard and

to the technical longevity of the PCI Local Bus architecture.

PCI-SIG membership is available to all applicants within the microcomputer industry.

Benefits of membership include:

 Ability to submit specification revisions and addendum proposals

 Participation in specification revisions and addendum proposals

 Automatically receive revisions and addenda

 Voting rights to determine the Board of Directors membership

 Vendor ID number assignment

 PCI technical support

 PCI support documentation and materials

 Participation in PCI-SIG sponsored trade show suites and events, conferences, and other

PCI Local Bus promotional activities

 Participation in the compliance program including participation at the “PCI Compliance

Workshops” and the opportunity to be included in the “PCI Integrator’s List”

An annual PCI-SIG membership costs US$3,000. This membership fee supports the

activities of PCI-SIG including the compliance program, PCI-SIG administration, and

vendor ID issuing and administration.

For information on how to become a PCI-SIG member or on obtaining PCI Local Bus

documentation, please contact:

PCI-SIG

5440 SW Westgate Drive

Suite 217

Portland, Oregon 97221

Phone: 800-433-5177 (Inside the U.S.)

503-291-2569 (Outside the U.S.)

Fax: 503-297-1090

e-mail administration@pcisig.com

http://www.pcisig.com

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