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AM389x Sitara ARM 微处理器技术参考手册
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"AM389x Sitara ARM 微处理器(MPUs)技术参考手册"
这份技术参考手册详细介绍了TI公司推出的AM389x Sitara ARM微处理器系列,该系列芯片集成了多种功能强大的模块,适用于各种嵌入式应用。手册涵盖的内容广泛,包括了芯片层面的资源、MPU子系统、内存映射、系统MMU、SGX530图形子系统以及设备中断等多个关键部分。
1. MPUSubsystem:MPU子系统是处理器的核心部分,它包括了ARM内核、AXI到OCP和I2异步桥接、中断控制器以及电源管理等组件。其中,MPU子系统的集成允许高效的数据传输和处理,而时钟和复位分布则确保了系统的稳定运行。
1.1 Introduction:这部分概述了MPU子系统的基本概念和设计目标。
1.2 Features:列出了AM389x Sitara MPU的主要特性,如高性能ARM Cortex-A8内核、丰富的外设接口等。
1.2.1 Integration:讨论了MPU子系统如何与整个芯片的其他部分协同工作。
1.2.2 Clock and Reset Distribution:详细描述了时钟和复位信号在子系统中的分布方式。
1.2.3 ARM Subchip:介绍ARM内核及其相关功能。
1.2.4 AXI2OCP and I2 Async Bridges:解释了这些桥接器如何连接不同总线接口,实现数据交换。
1.2.5 Interrupt Controller:阐述了中断控制器的角色,它是系统响应外部事件的关键部分。
1.2.6 Power Management:讨论了功耗管理和低功耗模式。
1.2.7 Host ARM Address Map和ARM Programming Model:定义了ARM内核的地址空间布局及编程模型。
1.3 Memory Map Summary:这部分详细列出了L3和L4内存地图,以及TILER扩展地址映射和Cortex-A8的内存映射,对于理解内存访问至关重要。
1.4 System MMU(内存管理单元):MMU提供了虚拟地址到物理地址的转换,支持硬件页面表管理,保证了多任务环境下内存的安全隔离。
1.4.1 MMU Overview:介绍了MMU的基本功能和作用。
1.4.2 MMU Integration:说明了MMU如何集成在AM389x系统中。
1.4.3 MMU Functional Description:深入解析了MMU的工作原理。
1.4.4 Low-level Programming Models:提供了MMU的编程模型和用法。
1.4.5 MMU Registers:列出了MMU的相关寄存器及其功能。
1.5 SGX530 Graphics Subsystem:这部分详细介绍了集成的SGX530图形处理器,用于图形渲染和用户界面支持。
1.5.1 SGX Overview:概述了SGX的架构和特性。
1.5.2 SGX Integration:描述了SGX如何与AM389x系统连接。
1.5.3 SGX Functional Description:详述了SGX的功能和操作。
1.5.4 SGX Registers:列出了SGX的寄存器,对调试和优化图形性能有重要作用。
1.6 Device Interrupts:这部分关注设备中断,是系统对外部事件响应的关键机制。
1.6.1 Interrupt Requests to Cortex-A8 MPU:解释了如何将中断请求传递给Cortex-A8内核。
AM389x Sitara ARM MPU具有高度集成的特性,包括强大的CPU、高效的内存管理和图形处理能力,以及精细的中断处理机制,适合于开发复杂的嵌入式应用。这份技术参考手册为开发者提供了全面的硬件理解和软件开发指导。
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17.3 Use Case................................................................................................................. 1620
17.3.1 PCIe Root Complex........................................................................................... 1620
17.3.2 PCIe End Point ................................................................................................ 1621
17.4 PCIe Registers........................................................................................................... 1622
17.4.1 Accessing Read-only Registers in Configuration Space................................................. 1622
17.4.2 Accessing EP Application Registers from PCIe RC ...................................................... 1622
17.4.3 Encoding of LTSSM State in DEBUG Registers .......................................................... 1623
17.4.4 PCIe Application Registers .................................................................................. 1624
17.4.5 Configuration Registers Common to Type 0 and Type 1 Headers ..................................... 1661
17.4.6 Configuration Type 0 Registers ............................................................................. 1664
17.4.7 Configuration Type 1 Registers ............................................................................. 1673
17.4.8 PCIe Capability Registers.................................................................................... 1681
17.4.9 PCIe Extended Capability Registers........................................................................ 1691
17.4.10 Message Signaled Interrupts Registers................................................................... 1700
17.4.11 Power Management Capability Registers ................................................................ 1702
17.4.12 Port Logic Registers......................................................................................... 1704
18 Power, Reset, and Clock Management (PRCM) Module........................................................ 1712
18.1 Introduction............................................................................................................... 1713
18.1.1 Device Power-Management Architecture Building Blocks .............................................. 1713
18.1.2 Module-Level Clock Management .......................................................................... 1714
18.1.3 Clock Domain.................................................................................................. 1717
18.1.4 Power Management .......................................................................................... 1719
18.2 Power Reset Clock Management Overview ......................................................................... 1721
18.2.1 Introduction .................................................................................................... 1721
18.2.2 Interfaces Description ........................................................................................ 1721
18.2.3 Power Control Interface ..................................................................................... 1721
18.2.4 FAPLL interface .............................................................................................. 1722
18.2.5 Device Control Interface ..................................................................................... 1722
18.2.6 Clocks Interface .............................................................................................. 1722
18.2.7 Resets Interface .............................................................................................. 1722
18.2.8 Modules Power Management Control Interface .......................................................... 1723
18.3 Device Modules and Power-Management Attributes List.......................................................... 1723
18.3.1 Active Power Domain Modules Attribute .................................................................. 1723
18.3.2 AlwaysOn Power Domain Modules Attribute ............................................................. 1723
18.3.3 Default Power Domain Modules Attribute ................................................................. 1725
18.3.4 SGX Power Domain Modules Attribute..................................................................... 1725
18.4 Clock Management ..................................................................................................... 1726
18.4.1 Terminology ................................................................................................... 1726
18.4.2 External Clock Sources to PRCM .......................................................................... 1726
18.4.3 Internal Clock Sources ....................................................................................... 1727
18.4.4 Clock Generation.............................................................................................. 1728
18.5 Reset Management ..................................................................................................... 1733
18.5.1 Overview ....................................................................................................... 1733
18.5.2 Reset Concepts and Definitions ............................................................................ 1733
18.5.3 Global Power-On (Cold) Reset ............................................................................. 1735
18.5.4 Global Warm Reset ........................................................................................... 1735
18.5.5 MPU Subsystem POR Sequence ........................................................................... 1736
18.5.6 MPU Subsystem Warm Sequence.......................................................................... 1737
18.6 Power Management..................................................................................................... 1737
18.6.1 Overview ....................................................................................................... 1737
18.6.2 Power Domains Management .............................................................................. 1739
18.6.3 Power Domain Transition Control .......................................................................... 1739
18.7 PRCM Registers......................................................................................................... 1740
16
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18.7.1 PRM_DEVICE ................................................................................................. 1741
18.7.2 CM_DEVICE ................................................................................................... 1743
18.7.3 OCP_SOCKET_PRM Device................................................................................ 1744
18.7.4 CM_DPLL Device ............................................................................................. 1745
18.7.5 CM_ACTIVE Device .......................................................................................... 1762
18.7.6 CM_DEFAULT Device........................................................................................ 1766
18.7.7 CM_SGX Device .............................................................................................. 1779
18.7.8 PRM_ACTIVE Device ........................................................................................ 1781
18.7.9 PRM_DEFAULT Device...................................................................................... 1783
18.7.10 PRM_SGX Device ........................................................................................... 1787
18.7.11 CM_ALWON Device......................................................................................... 1790
19 Real-Time Clock (RTC)..................................................................................................... 1848
19.1 Introduction............................................................................................................... 1849
19.1.1 Overview ....................................................................................................... 1849
19.1.2 Features ........................................................................................................ 1849
19.1.3 Functional Block Diagram.................................................................................... 1849
19.2 Architecture .............................................................................................................. 1850
19.2.1 Clock Source................................................................................................... 1850
19.2.2 Signal Descriptions............................................................................................ 1850
19.2.3 Interrupt Support .............................................................................................. 1851
19.2.4 Programming/Usage Guide .................................................................................. 1852
19.2.5 Scratch Registers ............................................................................................. 1856
19.2.6 Power Management .......................................................................................... 1856
19.2.7 Reset Considerations......................................................................................... 1856
19.3 RTC Registers ........................................................................................................... 1857
19.3.1 Seconds Register (SECONDS_REG) ...................................................................... 1858
19.3.2 Minutes Register (MINUTES_REG) ........................................................................ 1858
19.3.3 Hours Register (HOURS_REG) ............................................................................. 1859
19.3.4 Day of the Month Register (DAYS_REG).................................................................. 1859
19.3.5 Month Register (MONTHS_REG)........................................................................... 1860
19.3.6 Year Register (YEARS_REG) ............................................................................... 1860
19.3.7 Day of the Week Register (WEEKS_REG) ................................................................ 1861
19.3.8 Alarm Seconds Register (ALARM_SECONDS_REG) ................................................... 1861
19.3.9 Alarm Minutes Register (ALARM_MINUTES_REG)...................................................... 1862
19.3.10 Alarm Hours Register (ALARM_HOURS_REG)......................................................... 1862
19.3.11 Alarm Day of the Month Register (ALARM_DAYS_REG).............................................. 1863
19.3.12 Alarm Months Register (ALARM_MONTHS_REG) ..................................................... 1863
19.3.13 Alarm Years Register (ALARM_YEARS_REG).......................................................... 1864
19.3.14 Control Register (RTC_CTRL_REG)...................................................................... 1865
19.3.15 Status Register (RTC_STATUS_REG) ................................................................... 1867
19.3.16 Interrupt Register (RTC_INTERRUPTS_REG) .......................................................... 1868
19.3.17 Compensation (LSB) Register (RTC_COMP_LSB_REG).............................................. 1869
19.3.18 Compensation (MSB) Register (RTC_COMP_MSB_REG) ............................................ 1870
19.3.19 Oscillator Register (RTC_OSC_REG) .................................................................... 1871
19.3.20 Scratch Registers (RTC_SCRATCHx_REG) ............................................................ 1871
19.3.21 Kick Registers (KICK0R, KICK1R) ........................................................................ 1872
19.3.22 RTC Revision Register (RTC_REVISION) ............................................................... 1873
19.3.23 System Configuration Register (RTC_SYSCONFIG) ................................................... 1873
19.3.24 Wakeup Enable Register (RTC_IRQWAKEEN_0) ...................................................... 1874
20 Serial ATA (SATA) Controller............................................................................................ 1875
20.1 Introduction............................................................................................................... 1876
20.1.1 Purpose of the Peripheral .................................................................................... 1876
20.1.2 Features Supported........................................................................................... 1877
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20.1.3 Features Not Supported...................................................................................... 1877
20.1.4 Functional Block Diagram.................................................................................... 1878
20.1.5 Industry Standard(s) Compliance ........................................................................... 1878
20.1.6 Non-Industry Standard(s) Compliance ..................................................................... 1878
20.1.7 Terminology Used in this Document........................................................................ 1879
20.2 Architecture .............................................................................................................. 1880
20.2.1 Clock Control .................................................................................................. 1880
20.2.2 Signal Description ............................................................................................. 1881
20.2.3 DMA............................................................................................................. 1881
20.2.4 Transport Layer................................................................................................ 1882
20.2.5 FIFOs ........................................................................................................... 1882
20.2.6 Link Layer ...................................................................................................... 1882
20.2.7 PHY ............................................................................................................. 1882
20.2.8 Pin Multiplexing................................................................................................ 1882
20.2.9 Power Management .......................................................................................... 1882
20.2.10 Reset .......................................................................................................... 1883
20.2.11 Interfacing to Single and Multiple Devices ............................................................... 1883
20.2.12 Initialization ................................................................................................... 1883
20.2.13 Interrupt Support............................................................................................. 1885
20.2.14 EDMA Event Support ....................................................................................... 1886
20.3 Use Cases................................................................................................................ 1886
20.3.1 General Utilities: Structures and Subroutines Sample Program Uses ................................ 1886
20.3.2 Example on Initialization and Spinning Up Device........................................................ 1901
20.3.3 Example of DMA Write Transfer ............................................................................ 1903
20.3.4 Example of DMA Read Transfer ............................................................................ 1905
20.4 SATA Registers.......................................................................................................... 1906
20.4.1 HBA Capabilities Register (CAP) ........................................................................... 1908
20.4.2 Global HBA Control Register (GHC)........................................................................ 1909
20.4.3 Interrupt Status Register (IS) ................................................................................ 1910
20.4.4 Ports Implemented Register (PI) ............................................................................ 1911
20.4.5 AHCI Version Register (VS) ................................................................................. 1911
20.4.6 Command Completion Coalescing Control Register (CCC_CTL) ...................................... 1912
20.4.7 Command Completion Coalescing Ports Register (CCC_PORTS) .................................... 1913
20.4.8 BIST Active FIS Register (BISTAFR)....................................................................... 1914
20.4.9 BIST Control Register (BISTCR)............................................................................ 1914
20.4.10 BIST FIS Count Register (BISTFCTR).................................................................... 1917
20.4.11 BIST Status Register (BISTSR)............................................................................ 1917
20.4.12 BIST DWORD Error Count Register (BISTDECR) ...................................................... 1918
20.4.13 BIST DWORD Error Count Register (TIMER1MS)...................................................... 1918
20.4.14 Global Parameter 1 Register (GPARAM1R) ............................................................. 1919
20.4.15 Global Parameter 2 Register (GPARAM2R) ............................................................. 1920
20.4.16 Port Parameter Register (PPARAMR) .................................................................... 1921
20.4.17 Test Register (TESTR)...................................................................................... 1922
20.4.18 Version Register (VERSIONR) ............................................................................ 1923
20.4.19 ID Register (IDR) ............................................................................................ 1923
20.4.20 Port Command List Base Address Register (P#CLB) (# = 0 or 1) .................................... 1924
20.4.21 Port FIS Base Address Register (P#FB) (# = 0 or 1) ................................................... 1924
20.4.22 Port Interrupt Status Register (P#IS) (# = 0 or 1) ....................................................... 1925
20.4.23 Port Interrupt Enable Register (P#IE) (# = 0 or 1)....................................................... 1927
20.4.24 Port Command Register (P#CMD) (# = 0 or 1).......................................................... 1928
20.4.25 Port Task File Data Register (P#TFD) (# = 0 or 1)...................................................... 1931
20.4.26 Port Signature Register (P#SIG) (# = 0 or 1) ............................................................ 1931
20.4.27 Port Serial ATA Status Register (P#SSTS) (# = 0 or 1) ................................................ 1932
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20.4.28 Port Serial ATA Control Register (P#SCTL) (# = 0 or 1) ............................................... 1933
20.4.29 Port Serial ATA Error Register (P#SERR) (# = 0 or 1) ................................................. 1934
20.4.30 Port Serial ATA Active Register (P#SACT) (# = 0 or 1) ................................................ 1936
20.4.31 Port Command Issue Register (P#CI) (# = 0 or 1) ...................................................... 1936
20.4.32 Port Serial ATA Notification Register (P#SNTF) (# = 0 or 1) .......................................... 1937
20.4.33 Port DMA Control Register (P#DMACR) (# = 0 or 1) ................................................... 1938
20.4.34 Port PHY Control Register (P#PHYCR) (# = 0 or 1).................................................... 1940
20.4.35 Port PHY Status Register (P#PHYSR) (# = 0 or 1) ..................................................... 1944
20.4.36 Idle Register (IDLE) ......................................................................................... 1945
20.4.37 PHY Configuration Register 2 (PHYCFGR2) ............................................................ 1946
21 Timers ........................................................................................................................... 1947
21.1 Introduction............................................................................................................... 1948
21.1.1 Overview ....................................................................................................... 1948
21.1.2 Features ........................................................................................................ 1948
21.1.3 Functional Block Diagram.................................................................................... 1949
21.1.4 GP Timer External System Interface ....................................................................... 1950
21.2 Architecture .............................................................................................................. 1951
21.2.1 Functional Description ........................................................................................ 1951
21.2.2 Accessing Registers .......................................................................................... 1957
21.2.3 Posted Mode Selection....................................................................................... 1957
21.2.4 Write Registers Access....................................................................................... 1958
21.2.5 Read Registers Access....................................................................................... 1959
21.3 Timer Registers.......................................................................................................... 1960
21.3.1 TIDR Register.................................................................................................. 1961
21.3.2 TIOCP_CFG Register ........................................................................................ 1962
21.3.3 IRQ_EOI Register ............................................................................................. 1963
21.3.4 IRQSTATUS_RAW Register................................................................................. 1964
21.3.5 IRQSTATUS Register ........................................................................................ 1965
21.3.6 IRQENABLE_SET Register.................................................................................. 1966
21.3.7 IRQENABLE_CLR Register.................................................................................. 1967
21.3.8 IRQWAKEEN Register ....................................................................................... 1968
21.3.9 TCLR Register................................................................................................. 1968
21.3.10 TCRR Register............................................................................................... 1970
21.3.11 TLDR Register ............................................................................................... 1970
21.3.12 TTGR Register ............................................................................................... 1970
21.3.13 TWPS Register............................................................................................... 1971
21.3.14 TMAR Register............................................................................................... 1972
21.3.15 TCAR1 Register ............................................................................................. 1972
21.3.16 TSICR Register .............................................................................................. 1973
21.3.17 TCAR2 Register ............................................................................................. 1973
22 Watchdog Timer.............................................................................................................. 1974
22.1 Introduction............................................................................................................... 1975
22.1.1 Overview ....................................................................................................... 1975
22.1.2 Functional Block Diagram.................................................................................... 1975
22.1.3 Features ........................................................................................................ 1975
22.1.4 Watchdog Timer Environment ............................................................................... 1975
22.2 Architecture .............................................................................................................. 1976
22.2.1 Power Management .......................................................................................... 1976
22.2.2 Interrupts ....................................................................................................... 1976
22.2.3 General Watchdog Timer Operation........................................................................ 1976
22.2.4 Reset Context.................................................................................................. 1977
22.2.5 Overflow/Reset Generation .................................................................................. 1977
22.2.6 Prescaler Value/Timer Reset Frequency................................................................... 1977
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22.2.7 Triggering a Timer Reload ................................................................................... 1979
22.2.8 Start/Stop Sequence for Watchdog Timers (Using the WDT_WSPR Register) ...................... 1979
22.2.9 Modifying Timer Count/Load Values and Prescaler Setting ............................................. 1979
22.2.10 Watchdog Counter Register Access Restriction (WDT_WCRR Register) ........................... 1979
22.2.11 Watchdog Timer Interrupt Generation .................................................................... 1980
22.2.12 Watchdog Timers Under Emulation ....................................................................... 1981
22.2.13 Accessing Watchdog Timer Registers .................................................................... 1981
22.3 Low-Level Programming Model ....................................................................................... 1982
22.3.1 Global Initialization ............................................................................................ 1982
22.3.2 Operational Mode Configuration ............................................................................ 1982
22.4 Watchdog Timer Registers............................................................................................. 1984
22.4.1 WDT_WIDR Register ......................................................................................... 1985
22.4.2 WDT_WDSC Register ........................................................................................ 1985
22.4.3 WDT_WDST Register ........................................................................................ 1986
22.4.4 WDT_WISR Register ......................................................................................... 1986
22.4.5 WDT_WIER Register ......................................................................................... 1987
22.4.6 WDT_WCLR Register ........................................................................................ 1987
22.4.7 WDT_WCRR Register........................................................................................ 1988
22.4.8 WDT_WLDR Register ........................................................................................ 1988
22.4.9 WDT_WTGR Register ........................................................................................ 1988
22.4.10 WDT_WWPS Register ...................................................................................... 1989
22.4.11 WDT_WDLY Register ....................................................................................... 1990
22.4.12 WDT_WSPR Register....................................................................................... 1990
22.4.13 WDT_WIRQSTATRAW Register .......................................................................... 1991
22.4.14 WDT_WIRQSTAT Register ................................................................................ 1992
22.4.15 WDT_WIRQENSET Register .............................................................................. 1993
22.4.16 WDT_WIRQENCLR Register .............................................................................. 1994
23 UART/IrDA/CIR Module .................................................................................................... 1995
23.1 Introduction............................................................................................................... 1996
23.1.1 Main Features ................................................................................................. 1996
23.1.2 UART/Modem Functions ..................................................................................... 1997
23.1.3 IrDA Functions................................................................................................. 1997
23.1.4 CIR Features................................................................................................... 1997
23.2 Architecture .............................................................................................................. 1998
23.2.1 UART Signal Descriptions ................................................................................... 1998
23.2.2 UART/IrDA/CIR Mode Selection ............................................................................ 1998
23.2.3 UART Mode.................................................................................................... 1999
23.2.4 IrDA Mode...................................................................................................... 2003
23.2.5 CIR Mode ...................................................................................................... 2012
23.2.6 FIFO Management ........................................................................................... 2017
23.2.7 Interrupts ....................................................................................................... 2024
23.2.8 Sleep Modes................................................................................................... 2026
23.2.9 Idle Modes ..................................................................................................... 2026
23.2.10 Programmable Baud Rate Generator ..................................................................... 2027
23.3 UART Registers ......................................................................................................... 2030
23.3.1 Receiver Holding Register (RHR)........................................................................... 2031
23.3.2 Transmit Holding Register (THR) ........................................................................... 2031
23.3.3 Interrupt Enable Register (IER) - UART Mode ............................................................ 2032
23.3.4 Interrupt Enable Register (IER) - IrDA Mode .............................................................. 2033
23.3.5 Interrupt Enable Register (IER) - CIR Mode............................................................... 2034
23.3.6 Interrupt Identification Register (IIR) - UART Mode ...................................................... 2035
23.3.7 Interrupt Identification Register (IIR) - IrDA Mode ........................................................ 2036
23.3.8 Interrupt Identification Register (IIR) - CIR Mode ......................................................... 2037
20
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