
How to Optimize Usage of SAM S70/E70/V7x Architecture [APPLICATION NOTE]
Atmel-44047B-ATARM-Optimize-Usage-SAM-V71-V70-E70-S70-Architecture_Application-note_032016
1.3 Instruction and Data Cache
Cortex-M7 embeds an Instruction (I-cache) and Data cache (D-cache) to compensate wait state penalty when
executing code out of external memory (typically flash):
Instruction cache is 2-way associative, up to 64kB with optional ECC (16kB in SAM S70/E70/V7x)
Data cache is 4-way associative, up to 64kB with optional ECC (16kB in SAM S70/E70/V7x)
I-cache and D-cache are disabled by default and must be enabled by default in the application code.
1.4 Floating Point Unit
The Cortex-M7 processor can optionally integrate a Floating Point Unit (FPU). This FPU, corresponding to the
FPv5 extension, share the same instruction set as the previous version (FPv4) which was implemented on
Cortex-M4 processor and adds the double–precision operand support. It also introduces new instructions such
as rounding functions.
For more information on floating point instructions, you can refer to the Cortex-M7 Devices Generic User Guide
from ARM: http://infocenter.arm.com/help/topic/com.arm.doc.dui0646a/CHDHHAJF.html.
1.5 Memory Interface
As shown in Figure 1-1, Cortex-M7 core has four main memory interfaces.
1.5.1 AXI Master Interface
As said in introduction the Cortex-M7 processor features a new 64-bit interface running at processor frequency.
This interface is for both instruction and data accesses and dedicated for on-chip and off-chip memories and
devices (typically flash or RAM).
This interface has been optimized for performance: AXI accesses are not made in a predictable order as this
bus can re-order instruction or data to reduce latency and increase bandwidth.
If predictability is critical when executing some part of an application code, it is recommended to:
Configure the Memory Protection Unit (MPU) to define memory regions with proper attributes. For more
information on MPU configuration one can refer to the following application note:
http://www.atmel.com/Images/Atmel-42128-AT02346-Using-the-MPU-on-Atmel-Cortex-M3-M4-based-
Microcontroller_Application-Note.pdf
A typical MPU configuration example is also included in the software examples from the SAM
S70/E70/V7x Software Package.
Use memory barriers. More information can be found in a dedicated application note from ARM:
http://infocenter.arm.com/help/topic/com.arm.doc.dai0321a/DAI0321A_programming_guide_memory_ba
rriers_for_m_profile.pdf
1.5.2 AHB Peripheral Interface
The AHB Peripheral interface (AHBP) is dedicated to access low-latency peripherals rather than memory. Note
that AHBP does not support instruction fetch (which is performed through the AXI master interface), but only
data transfers. This interface has been added to avoid overloading the AXI master interface with additional
data transfers and so to increase the overall bandwidth.
Unlike AXI master interface, there is no optimization done and speculative access is not supported (e.g.
buffering is ordered). In addition bursts are not supported so only single access can be performed. For burst
access to peripheral it is recommended to use the DMA to do so.