Dialog DA14680 V3.0: 蓝牙低功耗4.2 SoC芯片技术手册

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本文档是Dialog半导体公司的DA14580 V3.0技术手册，专为低功耗蓝牙应用设计。该芯片是一款系统级芯片（System-on-Chip），集成了ARM Cortex-M0微处理器、内存、加密引擎、电源管理单元、数字和模拟外围设备、蓝牙智能（Bluetooth Smart）MAC引擎以及射频收发器，旨在为诸如运动手环这类穿戴设备提供高效能和长电池续航。核心特点包括： 1. 高性能处理器：基于ARM Cortex-M0架构，这款微处理器具备高达84 DMIPS的处理能力，支持灵活的内存配置，可以执行代码于嵌入式RAM、ROM或非易失性存储（如FLASH和OTP）。 2. 卓越的功耗管理：先进的电源管理单元允许芯片在主电池和辅助电池间切换，同时支持为外部设备供电。内置的充电器和状态电量检测功能使得芯片能够通过USB为可充电电池提供原生充电功能。 3. 动态时钟调整：一个外置PLL允许系统时钟在32kHz到96MHz之间动态调整，以满足不同应用对处理速度的需求，当系统处于空闲状态时，提供了多种优化睡眠模式来大幅减少能耗。 4. 蓝牙4.2兼容：芯片完全符合蓝牙4.2标准，确保了稳定的无线通信性能，并支持低功耗蓝牙技术，适合于对电池寿命敏感的应用场景。 5. 全面的硬件支持：集成的加密引擎提供了安全保障，数字和模拟外围设备为连接传感器和执行其他外围任务提供了基础，而射频收发器则确保了与蓝牙设备的高效通信。 DA14580 V3.0是一个高度集成且节能的解决方案，对于追求低功耗、便携性和可靠性的蓝牙设备制造商来说，是理想的开发平台。这份技术手册详细阐述了芯片的功能、规格和使用方法，有助于开发人员充分理解和利用其特性，实现高效能的硬件设计。

Datasheet Revision 3.0 28-February-2018

DA14680

Bluetooth Low Energy 4.2 SoC with FLASH

FINAL

3 System overview

3.1 INTERNAL BLOCKS

The DA14680 contains the following blocks:

ARM Cortex

M0 CPU with Wake-up Interrupt Con-

troller (WIC). This processor provides 0.9 dMIPS/MHz

and is used for implementing the higher layers of the

Bluetooth Low Energy protocol. It is also used for the

application requirements including controlling of the

power scheme of the system, reaching up to 86 dMIPs

if required. It is accompanied by a powerful cache con-

troller with configurable associativity, cache line size

and RAM size.

BLE 4.2 Core. This is the baseband hardware acceler-

ator for the Bluetooth Low Energy protocol.

Co-existence The CoEx sub-block implements a coex-

istence interface with external collocated modules

interfering with the 2.4GHz ISM band. A three wire

interface is realized to sync with the external modules

about the priority and the activity of the internal radio.

FLASH. This is an 8 Mbit low power Quad-SPI FLASH

which is used to directly execute code from (using the

CPU cache) or mirror the contents into the data RAM.

ROM. This is a 128 kB ROM containing the Bluetooth

Low Energy protocol stack as well as the boot code

sequence.

OTP. This is a 64 kB One Time Programmable memory

array, used to store the application code as well as the

Bluetooth Low Energy profiles. It also contains sys-

tem’s configuration and calibration values.

Data RAM. This is a 128 kB Data RAM (DataRAM)

which can be used for mirroring the program code from

the OTP when the system wakes/powers up or as a

normal data RAM when the system executes code

directly from OTP or QSPI FLASH. It also serves as

Data RAM for variables and various data that the proto-

col requires to be retained when system goes to sleep.

It comprises 5 physical RAM cells, all with content

retaining capability.

Cache/Tag RAM. This is a 16 kB data RAM used pri-

marily by the cache controller (CacheRAM). It is

accompanied by a Tag RAM. In mirrored mode the

CacheRAM can be used as an extension of the Data-

RAM, increasing the available memory to 144 kB.

Cache controller. This is an instruction cache control-

ler used for code execution directly from OTP or QSPI

FLASH, thus reducing accesses to these memories.

UART and UART2. Asynchronous serial interfaces.

UART2 implements hardware flow control with a FIFO

of 16 bytes depth.

SPI and SPI2. These are the serial peripheral inter-

faces with master/slave capability with a 16-bit wide

FIFO of 16 places.

I2C and I2C2. These are Master/Slave I2C interfaces

used for sensors and/or host MCU communication.

Each controller includes a FIFO of 4, 9-bit locations

General purpose (GP) ADC. This is a 10-bit analog-

to-digital converter with 8 external input channels and

averaging capabilities, which increase the effective

number of bits (ENOB) to 12.

Radio transceiver. This block implements the RF part

of the Bluetooth Low Energy protocol at 2.4 GHz.

Clock generator. This block is responsible for the

clocking of the system. It contains two crystal oscilla-

tors: one running at 16 MHz (XTAL16M), which is used

for the active mode of the system, and one running at

32.768 kHz (XTAL32K), which is used for the sleep

modes of the system.

There are also three RC oscillators available: a 16 MHz

and a 32 kHz oscillator (RC16M and RC32K) with low

precision (> 500 ppm) and a 11.7 kHz oscillator (RCX)

with higher precision (< 500 ppm).

The RCX oscillator can be used as a sleep clock

replacing the XTAL32K oscillator to further improve the

power dissipation, while reducing the bill of materials of

the system. The RC16M oscillator is used to provide a

clock for running SW already before the XTAL16M

oscillator has settled after power/wake up.

Additionally, a low power, short lock time PLL can be

activated to increase system’s speed to 96 MHz.

Software timers. This block contains a 16-bit general

purpose timer (Timer0) with PWM capability, a 16-bit

general purpose up/down timer (Timer1) with PWM

capability, which can operate at any clock even when in

sleep/deep sleep mode, and a 14-bit timer (Timer2),

which controls three PWM signals with respect to fre-

quency and duty cycle. The timer block also comprises

a dedicated timer implementing an LED breathing func-

tion with 256 steps granularity.

Wake-up controller. This is a timer for capturing exter-

nal events, that can be used as a wake-up trigger

based on a programmable number of external events

on any of the GPIO ports, or as a GPIO triggered inter-

rupt generator when the system is awake.

Quadrature decoder. This block decodes the pulse

trains from a rotary encoder to provide the step size

and the direction of movement of an external device.

Three axes (X, Y, Z) are supported.

Keyboard scanner. This circuit implements scanning

and debouncing of a keyboard matrix and generates

an interrupt upon a configurable action without the

need of CPU.

Infrared (IR) generator. This controller implements a

very flexible, low power, microcode based scheme for

IR protocols primarily used for remote controls.

AHB/APB bus. Implements the AMBA Lite version of

the AHB and APB specifications. Two different AHB

busses are used, one for the CPU and one for the

DMAs of the system. APB32 is implemented for the

Audio peripherals while APB16 is used for the other

peripheral blocks.

USB 1.1 FS Device. This is a 12 Mbit/s only USB

Datasheet Revision 3.0 28-February-2018

DA14680

Bluetooth Low Energy 4.2 SoC with FLASH

FINAL

device controller, which is mainly used for software

upgrades. It is also used for recharging the system’s

battery.

Cryptography blocks. The cryptography blocks con-

sist of a AES/HASH controller and an Elliptic Curve

Controller (ECC), accelerating any application security

requirements. A True Random Number Generator

(TRNG) is also provided enabling secure key genera-

tion.

DMA Engine. This is a general purpose DMA engine

with 8 channels that can be multiplexed to support data

fetching between peripherals and DataRAM.

Audio blocks. This part enables audio streaming by

means of a Pulse Density Modulation (PDM), a Sample

Rate Converter (SRC) and a Pulse Code Modulation

(PCM) interface. It can support 2 digital microphones or

2 digital loudspeakers using the PDM interface or con-

nect an external CoDec at the PCM/I2S interface.

Power management. A sophisticated power manage-

ment circuit with a Single Input Multiple Output (SIMO)

Buck DC-DC converter and several LDOs that can be

turned on/off via software. Extra pins are provided for

supplying external devices, even when the DA14680 is

in sleep/deep sleep mode. It also comprises a Con-

stant Current/Constant Voltage (CCCV) charger for the

battery charging and a state-of-charge fuel gauge cir-

cuit.

A more detailed description of each of the components

of the DA14680 is presented in the following sections.

3.2 FUNCTIONAL MODES

The DA14680 is optimised for embedded applications

such as health monitoring, sports measuring, human

interaction devices, etc. Customers are able to develop

and test their own applications. Upon completion of the

development, the application code can be programmed

into the embedded OTP or QSPI FLASH memory.

In principle, the system has two functional modes of

operation:

A. Mirrored mode. Application, profiles etc. are all

included in the OTP or QSPI FLASH. They will be mir-

rored at boot or wake-up time into the unified RAM,

which consists of both the CacheRAM and the Data-

RAM cells in a single, continuous memory space. Next,

the CPU starts executing from the unified RAM, which

is used for code as well as data.

During Mirrored mode the cache controller is totally

bypassed while all RAM cells (except for the Tag RAM)

are virtually moved into a continuous memory space.

B. Cached mode. This mode uses the memory

resources of the system as described in the block dia-

gram. The cached area can be OTP and/or the QSPI

FLASH memory space. Code is executed directly from

the OTP/FLASH through the cache controller, while

DataRAM is used for intermediate variables, stacks,

heaps and application data.

Mirrored mode or Cached mode should be configured

during initialisation of the system and not dynamically.

There are several different ways of executing code and

mapping the data segment of the system. The following

table provide an overview of the different possibilities

for BLE product use cases.

In addition, it is also possible to use parts of the Data-

RAM as code segments. In that case, parts of the code

can be placed in the DataRAM (a non-cacheable area),

while the system is operating in cached mode.

3.3 SYSTEM CONFIGURATION

The DA14680 contains a 64 kB One Time Programma-

ble (OTP) memory, which is used for storing the code

(as explained in Table 4) and for retaining the system’s

configuration data in a special OTP space called the

“OTP header”.

The OTP header occupies the last 712 words (64 bits

wide) in the OTP memory space. It is partitioned into

four sections that contain vital information for the sys-

tem, as illustrated in the following table.

Table 4: Memory configurations

Use case BLE stack code

Application and

profile code

BLE Exchange RAM

and data

Functional mode

BLE_01 ROM OTP DataRAM Mirrored

BLE_02 ROM FLASH DataRAM Mirrored

BLE_03 ROM OTP DataRAM Cached

BLE_04 ROM FLASH DataRAM Cached

BLE_05 FLASH FLASH DataRAM Cached

Datasheet Revision 3.0 28-February-2018

DA14680

Bluetooth Low Energy 4.2 SoC with FLASH

FINAL

Integrity of the data in the OTP header is guaranteed in

various ways. The OTP controller has an embedded

Error Correction Code hardware block, which can cor-

rect 1 bit error and detect 2 bit errors.

Furthermore, the Chip Configuration Section contains

mostly flags with redundancy over the whole 64-bit

word to ensure no mistaken value will be read. The flag

value is repeated over all bytes of the word.

The Trim and Calibration Settings Section comprises

the addresses and data values of the registers to be

configured after power/wake up. The OTP contains the

inverted values of both the address and the data val-

ues in the most significant 32-bit word. Reading from

OTP, checking and then storing the value into the

respective register is considered to be a fast and easy

task for software.

The Elliptic Curve Contents Section contains its own

CRC-16 checksum, while the actual OTP image (not

present in the header) is also optionally protected by a

CRC-16 checksum (Image CRC).

The QSPI FLASH Initialisation Section relies on the

OTP controller reports for integrity.

3.4 SYSTEM STARTUP PROCEDURE

After power-on or wake-up, a hardware state machine

is started, which resides in the Power Management

0x7F8EA48 8 QSPI Functions Bit0

0: Reset Function of QSPI FLASH is in BootROM

1: Reset Function of QSPI FLASH is in OTP

Bit1

0: Find “qQ” Function of QSPI FLASH is in

BootROM

1: Find “qQ” Function of QSPI FLASH is in OTP

Bit2

0: QSPI loader of QSPI FLASH is in BootROM

1: QSPI loader of QSPI FLASH is in OTP

0x7F8EA50 8 UART STX timing Defines the delay for booting from UART in units of

10 ms each.

0x7F8EA58 32 BDADDR Bluetooth Address

0x7F8EA78 384 Trim and Calibration Section (TCS)

0x7F8EA78 8 Trim and Calibration Register

Address

B7 to B5: Inverted address

B3 to B0: Address

0x7F8EA80 8 Trim and Calibration Register

Value

B7 to B5: Inverted data value

B3 to B0: Data value

0x7F8EA88 368 Trim values Contains all trim values and calibration values in

word pairs (Address, Value)

0x7F8EBF8 3072 Elliptic Curve Contents Section (ECS)

0x7F8EBF8 8 ECC image length and CRC B7 to B5: Inverted value of B3-B0

B3 to B2: Image CRC

B1 to B0: Image length in 32-bit words

0x7F8EC00 3064 ECC microcode Contains all ECC microcode for the Curves imple-

mentation

0x7F8F7F8 2048 QSPI FLASH Initialization Section (QFIS)

0x7F8F7F8 8 Address for the QSPI Reset

code

B7-B5: Section length (Bytes)

B3-B0: Address

0x7F8F800 8 Address for the QSPI "pP"

identification code

B7-B5: Section length (Bytes)

B3-B0: Address

0x7F8F808 8 Address for the QSPI Loader

code

B7-B5: Section length (Bytes)

B3-B0: Address

0x7F8F810 8 Address for the QSPI wake up

uCode

B7-B5: Section length (Bytes)

B3-B0: Address

0x7F8F818 2016 Contains all QSPI related code

segments

Table 5: OTP header details

Address Size (B) Field name Description

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