© Science China Press and Springer-Verlag Berlin Heidelberg 2010 csb.scichina.com www.springerlink.com
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SPECIAL TOPICS:
Computer Science & Technology
October 2010 Vol.55 No.29: 3363–3371
doi: 10.1007/s11434-010-4118-z
Computationally efficient locality-aware interconnection topology
for multi-processor system-on-chip (MP-SoC)
Haroon-Ur-Rashid Khan
*
, SHI Feng, JI WeiXing, GAO YuJin, WANG YiZhuo, LIU CaiXia,
DENG Ning & LI JiaXin
School of Computer Sicence and Technology, Beijing Institute of Technology, Beijing 100081, China
Received March 16, 2009; accepted May 1, 2010
This paper evaluates the Triplet Based Architecture, TriBA – a new idea in chip multiprocessor architectures and a class of Direct
Interconnection Network (DIN). TriBA consists of a 2D grid of small, programmable processing units, each physically connected
to its three neighbors so that advantageous features of group locality can be fully and efficiently utilized. Any communication
model can be well characterized by locality properties and, any topology has its intrinsic, structural, locality characteristics. We
propose a new criterion in performance evaluation that is based on the concept of locality in an interconnection network, the
“lower layer complete connect”. Our proposed criterion depicts how completely a processing node is connected to all its
neighbors. TriBA is compared with 2D Mesh and Binary Tree as static interconnection network. The comparison / evaluation is
enumerated from three orthogonal view points, viz., computational speed, physical layout and cost. Our analysis concludes that
TriBA is computationally efficient interconnection strategy that exploits group locality in processing nodes.
multiprocessor, locality, interconnection network, VLSI layout, performance evaluation
Citation: Khan H U R, Shi F, Ji W X, et al. Computationally efficient locality-aware interconnection topology for multi-processor system-on-chip (MP-SoC).
Chinese Sci Bull, 2010, 55: 3363−3371, doi: 10.1007/s11434-010-4118-z
Multiprocessor Systems on Chip (MPSoC) combine the
advantages of parallel computing of multiprocessors with
single chip integration of SoCs. MPSoCs are employed in
embedded system that requires high performance data
processing capabilities [1–4]. Examples include network
processors (NPs), parallel multimedia processors (PMPs)
and other application specific array processors (ASAPs).
Improvements in semiconductor technology have made it
possible to include multiple processor cores on a single die.
Chip Multi-Processors (CMP) are an attractive choice for
future billion transistor architectures due to their low design
complexity, high clock frequency, and high throughput.
Multi-Processor (MP-SoC) platforms are emerging as the
latest trend in SoC design. These MP-SoCs consist of a
large number of Intellectual Property (IP) blocks in the form
of functionally homogenous/heterogeneous embedded
*Corresponding author (email: haroon@bit.edu.cn)
processors. In this new design paradigm, IP blocks need to
be integrated using a structured interconnect template, for
example, according to high-performance parallel computing
architectures. A formal evaluation process is required before
adopting a specific parallel architecture to SoC domain
[1,5].
Complex Systems on Chip (SoCs) can be realized con-
sisting of billions of transistors in 65 nm technology [5,6].
The emergence of SoC platforms consisting of large, het-
erogeneous sets of embedded processors is imminent
[1,2,6]. A key focus of such multiprocessors SoC platform
is the interconnect topology. Therefore, the on-chip inter-
connect topology should resemble the interconnect archi-
tecture of high-performance parallel computing systems
[1,2]. Many interconnection networks for on-chip multi-
processor architecture have been proposed in the literature,
over the past three decades. Extensive accounts of these
networks and their performance evaluation have been re-