UCD3138A数字控制器技术规格与应用

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"TI-UCD3138A.pdf 是德州仪器(TI)推出的一款高性能数字控制器，专为隔离电源设计，具有高度集成的数字控制功能。该控制器支持多种控制策略，包括二极管仿真、同步镇流器软启停、非线性控制等，适用于复杂的电源系统。其特性包括低待机功率、初级侧电压感应、电流感应、磁通均衡、相电流均衡等。此外，UCD3138A还具备丰富的故障保护功能，如逐周期电流限制、可编程故障输入、自动分辨率选择等，并且具有高速模拟比较器和数字比较器。控制器内置了16MHz误差模数转换器(EADC)、10位有效数模转换器(DAC)以及14通道、12位的通用ADC，提供高分辨率的DPWM输出和多个设备间的波形同步。此外，它还包含了31.25MHz的32位ARM7TDMI-S处理器，支持现场固件升级，并且具备通信接口如I2C和PMBus，便于系统监控和管理。" UCD3138A是一款高级数字电源控制器，其关键特点包括： 1. **数字控制**：支持多达3个独立反馈环路的数字控制，可以灵活地调整电源性能。 2. **电源管理**：具有同步镇流器软启停功能，优化了电源效率和稳定性。 3. **感应技术**：通过初级侧电压感应和铜走线电流感应，实现了精确的系统监测。 4. **故障保护**：提供多种保护机制，如逐周期电流限制和可编程故障输入，确保系统安全运行。 5. **硬件加速**：内置PID硬件加速器，提高了响应速度。 6. **高精度采样**：高速ADC和比较器，允许高分辨率的信号处理和故障检测。 7. **DPWM输出**：8个高分辨率的DPWM输出，支持250ps的脉宽分辨率，可进行精细的功率调节。 8. **同步能力**：多个UCD3138A设备间的DPWM波形同步，保证了多相电源的一致性。 9. **处理器核心**：32位ARM7TDMI-S处理器，支持2MHz的切换频率，提供了强大的计算能力。 10. **通信接口**：支持I2C和PMBus，方便与系统其他部分进行通讯和控制。这款控制器在电源设计中扮演着重要角色，其丰富的功能和灵活性使其成为复杂电源系统的理想选择。通过其强大的控制和监测能力，可以实现精确的电源管理，同时保证了系统的稳定性和可靠性。

UCD3138A

www.ti.com.cn

ZHCSDJ8A –MARCH 2015–REVISED APRIL 2015

Electrical Characteristics (continued)

V33A = V33D = V33DIO = 3 V to 3.6 V; 1 μF from BP18 to DGND, T

= –40°C to 125°C (unless otherwise noted)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

POWER ON RESET AND BROWN OUT (V33D pin, See Figure 5-4)

VGH Voltage good high 2.7 V

VGL Voltage good low 2.5 V

res

Voltage at which I

RESET

signal is valid 0.8 V

Time delay after power is good or

POR

1 ms

RESET relinquished

Internal signal warning of brownout

Brownout 2.9 V

conditions

TEMPERATURE SENSOR

(7)

TEMP

Voltage range of sensor 1.46 2.44 V

Voltage resolution V/°C 5.9 mV/ºC

Temperature resolution °C per bit 0.1034 ºC/LSB

Accuracy

(7)(8)

–40°C to 125°C –10 ±5 10 ºC

Temperature range –40°C to 125°C –40 125 ºC

TEMP

Current draw of sensor when active 30 μA

Turn on time / settling time of sensor 100 μs

AMB

Ambient temperature Trimmed 25°C reading 1.85 V

ANALOG COMPARATOR

DAC Reference DAC Range 0 2.5 V

Reference Voltage 2.478 2.5 2.513 V

Bits 7 bits

INL

(7)

–0.42 0.21 LSB

DNL

(7)

0.06 0.12 LSB

Offset –5.5 19.5 mV

Time to disable DPWM output based on 0

V to 2.5 V step input on the analog 150 ns

comparator.

(1)

Reference DAC buffered output load

(9)

0.5 1 mA

Buffer offset (–0.5 mA) 0.3 V < DAC < 2.17 V 0 10 mV

Buffer offset (1.0 mA) 0.3 V < DAC < 2.17 V –10 0 mV

(7) Characterized by design and not production tested.

(8) Ambient temperature offset value should be used from the TEMPSENCTRL register to meet accuracy.

(9) Available from reference DACs for comparators D, E, F, and G.

5.5 Thermal Characteristics

UCD3138A UCD3138A

THERMAL METRIC

(1)

UNIT

64 PIN QFN 40 PIN QFN

(RGC) (RMH)

θJA

Junction-to-ambient thermal resistance 25.1 31.0

θJC(top)

Junction-to-case (top) thermal resistance 10.5 16.5

θJB

Junction-to-board thermal resistance 4.6 6.3

°C/W

Junction-to-top characterization parameter 0.2 0.2

Junction-to-board characterization parameter 4.6 6.3

θJC(bot)

Junction-to-case (bottom) thermal resistance 1.2 1.1

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953

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Product Folder Links: UCD3138A

Error ADC

(Front End)

Filter

Digital

PWM

EAP

EAN

DPWMA

DPWMB

UCD3138A

ZHCSDJ8A –MARCH 2015–REVISED APRIL 2015

www.ti.com.cn

5.8 Peripherals

5.8.1 Digital Power Peripherals (DPPs)

At the core of the UCD3138A controller are three DDPs. Each DPP can be configured to drive from one to

eight DPWM outputs. Each DPP consists of:

• Differential input error ADC (EADC) with sophisticated controls

• Hardware accelerated digital 2-pole/2-zero PID based compensator

• Digital PWM module with support for a variety of topologies

These can be connected in many different combinations, with multiple filters and DPWMs. They are

capable of supporting functions like input voltage feed forward, current mode control, and constant

current/constant power, and so on. The simplest configuration is shown in the following figure:

5.8.1.1 Front End

Figure 5-5 shows the block diagram of the front end module. It consists of a differential amplifier, an

adjustable gain error amplifier, a high speed flash analog to digital converter (EADC), digital averaging

filters and a precision high resolution set point DAC reference. The programmable gain amplifier in concert

with the EADC and the adjustable digital gain on the EADC output work together to provide 9 bits of range

with 6 bits of resolution on the EADC output. The output of the Front End module is a 9-bit sign extended

result with a gain of 1 LSB / mV. Depending on the value of AFE selected, the resolution of this output

could be either 1, 2, 4 or 8 LSBs. In addition each EADC has the ability to automatically select the AFE

value such that the minimum resolution is maintained that still allows the voltage to fit within the range of

the measurement. The EADC control logic receives the sample request from the DPWM module for

initiating an EADC conversion. EADC control circuitry captures the EADC-9-bit-code and strobes the

digital compensator for processing of the representative error. The set point DAC has 10 bits with an

additional 4 bits of dithering resulting in an effective resolution of 14 bits. This DAC can be driven from a

variety of sources to facilitate things like soft start, nested loops, and so on. Some additional features

include the ability to change the polarity of the error measurement and an absolute value mode which

automatically adds the DAC value to the error.

It is possible to operate the controller in a peak current mode control configuration; an EADC is

recommended for implementing peak current mode control. In this mode, topologies like a phase shifted

full bridge converter can be controlled to maintain transformer flux balance. The internal DAC can be

ramped at a synchronously controlled slew rate to achieve a programmable slope compensation. This

eliminates the sub-harmonic oscillation as well as improves input voltage feed-forward performance. A0 is

a unity gain buffer used to isolate the peak current mode comparator. The offset of this buffer is specified

in Section 5.4.

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