威廉·斯托林斯《计算机组织与体系结构》英文版答案详解

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《计算机组织与体系结构：设计为性能》第七版是由William Stallings所著的一本经典的计算机科学教材。这本书详细探讨了计算机系统的各个关键组成部分及其设计原则，旨在帮助读者理解计算机如何实现高效运作。以下是章节概览及主要知识点： 1. **计算机进化与性能** (Chapter 2): 本章回顾了计算机的发展历程，从早期的机械计算装置到现代电子计算机，讲述了技术进步如何推动性能提升。性能指标如速度、存储容量和能源效率等内容在此被深入分析。 2. **计算机功能与互连** (Chapter 3): 这里讨论了计算机硬件组件如何协同工作，包括处理器、输入输出设备和总线架构等，以及它们之间的接口设计，以确保数据传输和指令执行的高效。 3. **缓存内存** (Chapter 4): 缓存是提高系统速度的关键部分，作者解释了层次式存储结构，如L1、L2、L3缓存的工作原理，以及它们如何通过减少访问主存时间来优化性能。 4. **内部存储器** (Chapter 5): 内存单元的设计，包括RAM（随机存取存储器）和ROM（只读存储器）的特性和组织，以及现代多核处理器中的共享内存模型。 5. **外部存储器** (Chapter 6): 详细讲解硬盘、固态硬盘、光盘和其他外部存储介质，阐述其容量、速度和数据持久性的区别，以及文件系统在数据管理中的作用。 6. **输入/输出** (Chapter 7): 讲述I/O设备的类型、操作方式，以及操作系统如何管理I/O请求，确保数据在主机和外设间的可靠传输。 7. **操作系统支持** (Chapter 8): 描述操作系统如何协调硬件资源，提供抽象层以简化编程，以及它在性能优化、内存管理和调度方面的角色。 8. **计算机算术** (Chapter 9): 包括二进制运算、浮点数表示与运算，以及错误检测和纠正机制，这些都是保证计算精度的基础。 9. **指令集：特性和功能** (Chapter 10): 指令集架构（ISA）的重要性被深入剖析，包括指令格式、寻址方式和指令集的扩展性，以及不同CPU架构对性能的影响。每章都配以详细的解答（Solution Manual），涵盖了复习问题和作业题，为学生和学习者提供了宝贵的实践参考。在阅读过程中，如果发现任何错误或疑问，作者鼓励读者通过电子邮件与他联系，以确保教材的准确性和完整性。通过学习这本书，读者将获得扎实的计算机体系结构理论基础，以及实际应用中的设计原则和策略。

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Offset

SetTag

20 bits

8 4

Decoder

Comp1

Comp2

Comp3

Comp4

Set 0

Set 1

Set 255

•

Set

255

Tag (20) 4 DWs

Hit

Example: doubleword from location ABCDE8F8 is mapped onto: set 143, any

line, doubleword 2:

(1000)A B C D E (1111) (1000)

8 F 8

Set = 143

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4.9 a. The bits are set according to the following rules with each access to the set:

1. If the access is to L0 or L1, B0 ← 1.

2. If the access is to L0, B1 ← 1.

3. If the access is to L1, B1 ← 0.

4. If the access is to L2 or L3, B0 ← 0.

5. If the access is to L2, B2 ← 1.

6. If the access is to L3, B2 ← 0.

The replacement algorithm works as follows (Figure 4.15): When a line must be

replaced, the cache will first determine whether the most recent use was from

L0 and L1 or L2 and L3. Then the cache will determine which of the pair of

blocks was least recently used and mark it for replacement. When the cache is

initialized or flushed all 128 sets of three LRU bits are set to zero.

b. The 80486 divides the four lines in a set into two pairs (L0, L1 and L2, L3). Bit

B0 is used to select the pair that has been least-recently used. Within each pair,

one bit is used to determine which member of the pair was least-recently used.

However, the ultimate selection only approximates LRU. Consider the case in

which the order of use was: L0, L2, L3, L1. The least-recently used pair is (L2,

L3) and the least-recently used member of that pair is L2, which is selected for

replacement. However, the least-recently used line of all is L0. Depending on

the access history, the algorithm will always pick the least-recently used entry

or the second least-recently used entry.

c. The most straightforward way to implement true LRU for a four-line set is to

associate a two bit counter with each line. When an access occurs, the counter

for that block is set to 0; all counters with values lower than the original value

for the accessed block are incremented by 1. When a miss occurs and the set is

not full, a new block is brought in, its counter is set to 0 and all other counters

are incremented by 1. When a miss occurs and the set is full, the block with

counter value 3 is replaced; its counter is set to 0 and all other counters are

incremented by 1. This approach requires a total of 8 bits.

In general, for a set of N blocks, the above approach requires 2N bits. A

more efficient scheme can be designed which requires only N(N–1)/2 bits. The

scheme operates as follows. Consider a matrix R with N rows and N columns,

and take the upper-right triangular portion of the matrix, not counting the

diagonal. For N = 4, we have the following layout:

R(1,2)

R(1,3)

R(1,4)

R(2,3)

R(2,4)

R(3,4)

When line I is referenced, row I of R(I,J) is set to 1, and column I of R(J,I) is set

to 0. The LRU block is the one for which the row is entirely equal to 0 (for those

bits in the row; the row may be empty) and for which the column is entirely 1

(for all the bits in the column; the column may be empty). As can be seen for N

= 4, a total of 6 bits are required.

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CABBE = 1100 1010 1011 1011 1110

Word offset = 1110 = E

Slot = 1010 1011 1011 = ABB

Tag = 1100 = C

b. We need to pick any address where the slot is the same, but the tag (and

optionally, the word offset) is different. Here are two examples where the slot

is 1111 1111 1111

Address 1:

Word offset = 1111

Slot = 1111 1111 1111

Tag = 0000

Address = 0FFFF

Address 2:

Word offset = 0001

Slot = 1111 1111 1111

Tag = 0011

Address = 3FFF1

c. With a fully associative cache, the cache is split up into a TAG and a

WORDOFFSET field. We no longer need to identify which slot a memory block

might map to, because a block can be in any slot and we will search each cache

slot in parallel. The word-offset must be 4 bits to address each individual word

in the 16-word block. This leaves 16 bits leftover for the tag.

F0010

Word offset = 0h

Tag = F001h

CABBE

Word offset = Eh

Tag = CABBh

d. As computed in part a, we have 4096 cache slots. If we implement a two -way

set associative cache, then it means that we put two cache slots into one set.

Our cache now holds 4096/2 = 2048 sets, where each set has two slots. To

address these 2048 sets we need 11 bits (211 = 2048). Once we address a set, we

will simultaneously search both cache slots to see if one has a tag that matches

the target. Our 20-bit address is now broken up as follows:

Bits 0-3 indicate the word offset

Bits 4-14 indicate the cache set

Bits 15-20 indicate the tag

F0010 = 1111 0000 0000 0001 0000

Word offset = 0000 = 0

Cache Set = 000 0000 0001 = 001

Tag = 11110 = 1 1110 = 1E

CABBE = 1100 1010 1011 1011 1110

Word offset = 1110 = E

Cache Set = 010 1011 1011 = 2BB

Tag = 11001 = 1 1001 = 19

4.13 Associate a 2-bit counter with each of the four blocks in a set. Initially, arbitrarily

set the four values to 0, 1, 2, and 3 respectively. When a hit occurs, the counter of

the block that is referenced is set to 0. The other counters in the set with values

originally lower than the referenced counter are incremented by 1; the remaining

counters are unchanged. When a miss occurs, the block in the set whose counter

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