GPP平台上的IEEE 802.11n LDPC码实现：高速编码与解码优化

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本文是一篇研究论文，发表在2013年的国际计算机通信大会（ICCT）上，标题为《基于通用处理器的IEEE 802.11n LDPC代码实现》。作者是来自北京邮电大学通用无线通信国家重点实验室的肖涵、 Kai Niu 和 Zhiqiang He。随着通用处理器（GPP）软定义无线电（SDR）平台因其可编程性和灵活性受到广泛关注，他们将目光投向了如何在这些平台上实现高速无线协议，如IEEE 802.11标准系列（包括802.11a/b/g）。 IEEE 802.11n标准引入了低密度奇偶校验（LDPC）码作为选项，以提供接近香农极限的高性能纠错能力，尤其是在高吞吐量（HT）模式下。在通用处理器平台上完成IEEE 802.11n LDPC编码和解码的实现是本文的核心内容。为了充分利用现代处理器架构的特点来加速数据处理，文章着重探讨了如何利用大容量低延迟缓存存储查找表，以及如何通过指令级并行性、流水线优化和向量化技术来提升编码和解码的性能。论文中，作者可能讨论了以下关键知识点： 1. **通用处理器在SDR中的应用**：GPP在SDR系统中的优势，如灵活性和易于定制，使得它们成为实现复杂无线标准的理想选择。 2. **IEEE 802.11n LDPC码的重要性**：作为一种高效纠错编码，LDPC码对于提高数据传输的可靠性至关重要，特别是在追求高数据速率的环境中。 3. **硬件加速**：利用处理器特性，如缓存和流水线设计，来优化LDPC编码和解码算法，以减少延迟并提高处理速度。 4. **软件优化**：可能涉及编程技巧，如并行计算和向量化，以充分利用多核处理器的计算资源，进一步提升编码和解码的性能。 5. **实际应用与挑战**：在实际的GPP平台上实施这种复杂算法可能遇到的挑战，如功耗管理、代码效率和兼容性问题。这篇论文不仅提供了关于如何在通用处理器上实现IEEE 802.11n LDPC编码和解码的具体方法，还可能为其他研究人员和工程师开发高速、高效的无线通信解决方案提供了有价值的技术参考。

Proceedings of ICCT2013

Implementation of IEEE 802.11n LDPC Codes Based on

General Purpose Processors

Xiao Han, Kai Niu, Zhiqiang He

Key Lab of Universal Wireless Communications, Ministry of Education,

Beijing University of Posts and Telecommunications, Beijing 100876, China

15810537980@139.com

Abstract: Recently, General-purpose processor (GPP)

soft defined radio (SDR) platforms have drawn great

attention for their programmability and flexibility, and

some high-speed wireless protocol stacks (e.g., IEEE

802.11a/b/g) have been implemented on them using

commodity general-purpose PCs. Low-density

parity-check (LDPC) codes are optionally used in IEEE

802.11n high throughput (HT) system as a

high-performance error correcting code instead of

convolutional codes for the near Shannon limit

performance. In order to complete the implementation of

IEEE 802.11n on SDR platforms, this paper presents the

encoding and decoding of IEEE 802.11n LDPC codes

on GPPs. We extensively use the features of

contemporary processor architectures to accelerate data

processing, including large low-latency caches to store

lookup tables and SIMD processing on GPPs. Layered

decoding is used in this paper, which can significantly

reduce the number of iterations and is well suited to

using SIMD instructions. The implementation results

show that the throughput can meet the protocol timing

requirement under the performance premise.

Keywords: Low-density parity-check (LDPC) codes;

layered decoding; General-purpose processor (GPP);

IEEE 802.11n

1 Introduction

The increasing demand of high data-rate and reliability

in modern wireless communication systems requires

high-performance error-correction schemes.

Low-density parity-check (LDPC) codes [1] are among

the best candidates to meet these requirements for

next-generation wireless communication standards. In

particular, quasi-cyclic (QC) LDPC codes [2] enjoy high

decoding throughput at relatively low implementation

complexity, and has been considered in different

wireless standards, such as IEEE 802.16e [3] and IEEE

802.11n [4].

Owing to the special structure of the IEEE 802.11n

LDPC parity check matrices, the encoder can be

performed very efficiently. As this paper shows, the

encoder of IEEE 802.11n LDPC can be simplified into

matrix multiplier and adder. The decoder of LDPC in

this paper is based on the concept of turbo decoding

message passing (TDMP), which is also called layered

decoding [5]. Compared to standard two-phase message

passing (TPMP), TDMP offers 2x throughput as the

number of iterations decreases by 50%. TDMP

architecture also saves the memory needed to store the

variable node messages and the channel log-likelihood

ratios (LLR).

Software defined radio (SDR) holds the promise of fully

programmable wireless communication systems,

effectively supplanting current technologies which have

the lowest communication layers implemented primarily

in fixed, custom hardware circuits [6]. Moreover, SDR

platforms are based on general-purpose processor (GPP)

architectures, such as commodity PCs. Developers

program to familiar architecture and environment using

sophisticated programming and debugging tools.

In this paper, we implement the encoding and decoding

of IEEE 802.11n LDPC on GPPs. The features of

contemporary processor architectures are extensively

exploited to accelerate data processing. First, we use

lookup tables (LUTs) widely, trading off computation

for memory. These LUTs substantially reduce the

computational requirements, while at the same time

taking advantage of the large, low-latency caches on

modern GPPs. Second, in order to further accelerate data

processing with data-level parallelism, we heavily use

the Single Instruction Multiple Data (SIMD) extensions

in modern GPPs, which can extremely speed up the data

processing. It should be noted that since the number of

nonnegative elements is not invariable for different rows

of a prototype matrix, GPPs enjoy the advantage of

flexibility over hardware platforms in the

implementation of decoder.

The rest of the paper is organized as follows. Section II

introduces the structure of QC-LDPC in IEEE 802.11n

briefly. Section III presents the implementation of IEEE

802.11n LDPC encoder based on GPPs. Then, the

implementation of decoder is described specifically in

Section IV. Section V gives the implementation results.

Finally, we conclude the paper in section VI.

2 LDPC Codes for IEEE 802.11n



,NK

LDPC code is specified by the parity-check

matrix

whose size is

MN

. Since the LDPC

codes for IEEE 802.11n are based on block-structured

QC-LDPC codes, the parity-check matrix can be

partitioned into square submatrices of size

ZZ

, where

____________________________________

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