Si446x API 命令与配置手册

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"AN625_Si446x 命令描述手册1提供了Si446x系列芯片的API描述，涵盖了控制和配置该芯片所需的命令和属性。" 在Si446x的API中，有两类主要的命令：Boot Commands（启动命令）和Common Commands（通用命令）。这些命令用于设备的初始化、配置和信息获取。 Boot Commands主要用于设备的启动和模式选择。例如，0x02的POWER_UP命令用于设备上电并选择工作模式，可以设定设备进入不同的操作功能状态。 Common Commands则包含了一系列基础和通用的操作： 1. 0x00 NOP (无操作命令)：执行此命令后，设备不做任何处理，常用于调试时的占位。 2. 0x01 PART_INFO：报告设备的基本信息，如芯片ID、版本等，帮助识别和验证设备。 3. 0x10 FUNC_INFO：返回设备的功能修订信息，提供设备的软件版本和特性详情。 4. 0x11 SET_PROPERTY：设置设备的某个属性值，用于个性化配置芯片的各项参数。 5. 0x12 GET_PROPERTY：读取设备的属性值，用于检查当前配置或诊断。 6. 0x13 GPIO_PIN_CFG：配置GPIO引脚，实现灵活的输入输出控制。 7. 0x14 GET_ADC_READING：获取ADC（模拟数字转换器）的读数，用于读取环境信号或其他模拟信号。 8. 0x15 FIFO_INFO：访问发送和接收FIFO（先进先出）的计数，并可以重置FIFO，管理数据传输。 9. 0x16 PACKET_INFO：提供关于最后接收到的包的信息，还可以选择性地覆盖字段长度，适应不同协议需求。 10. 0x17 IRCAL：校准图像抑制，优化射频接收性能。 11. 0x18 PROTOCOL_CFG：设置芯片以支持特定的通信协议，如SPI、I2C等。 12. 其他未列出的命令，如0x19至0x1F，可能包括更多的配置和控制选项。这些命令是开发基于Si446x的无线通信系统的关键，通过它们可以精细调整设备以满足应用需求，如设置发射功率、频率、数据速率，以及处理接收数据等。对于理解Si446x的工作原理和进行系统级集成，深入掌握这些命令和属性的用法至关重要。标签"hive"可能是指文档管理系统或者表示该资料在一个类似蜂巢状的结构中，但具体含义需要结合上下文理解。由于这部分信息与Si446x的命令描述手册内容关联性不强，故在此不做进一步解释。

AN625

16 Rev. 0.1

3.2.6. GPIO_PIN_CFG

 Summary: Configures the GPIO pins

 Command Stream

 Reply Stream

 Parameters:

GPIO0_PULL_CTL

0 = Disable pullup. Recommended setting if pin is driven.

1 = Enable pullup.

GPIO0_MODE[5:0]

0 = Do not modify the behavior of this pin.

1 = Input and output drivers disabled.

2 = CMOS output driven low.

3 = CMOS output driven high.

4 = CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g., TX Direct Mode Data In).

The actual function of this pin is controlled by other properties.

5 = 32 kHz clock. Outputs 32 kHz clock selected using GLOBAL_CLK_CFG:CLK_32K_SEL. Output low if the

32 kHz clock is not enabled.

6 = BOOT_CLK. Outputs boot clock. This will only output when the device is in SPI ACTIVE state because that is the

only time the boot clock is active.

GPIO_PIN_CFG Command7 6 543210

CMD 0x13

GPIO0 0 GPIO0_PULL_CTL GPIO0_MODE[5:0]

GPIO1 0 GPIO1_PULL_CTL GPIO1_MODE[5:0]

GPIO2 0 GPIO2_PULL_CTL GPIO2_MODE[5:0]

GPIO3 0 GPIO3_PULL_CTL GPIO3_MODE[5:0]

NIRQ 0 NIRQ_DRV_PULL NIRQ_MODE[5:0]

SDO 0 SDO_PULL_CTL SDO_MODE[5:0]

GEN_CONFIG 0 DRV_STRENGTH[1:0] 00000

GPIO_PIN_CFG Reply 7 6 5 43210

CTS CTS[7:0]

GPIO0 GPIO0_STATE X GPIO0r_[5:0]

GPIO1 GPIO1_STATE X GPIO1r_[5:0]

GPIO2 GPIO2_STATE X GPIO2r_[5:0]

GPIO3 GPIO3_STATE X GPIO3r_[5:0]

NIRQ NIRQSTATE X NIRQr_[5:0]

SDO SDOSTATE X SDOr_[5:0]

GEN_CONFIG X DRV_STRENGTH[1:0] XXXXX

AN625

Rev. 0.1 17

7 = Divided MCU clock. Outputs divided clock. Output divided boot clock in SPI ACTIVE state, Output low while in

SLEEP state as the divided clock source is not running, and Output divided XTAL in all other states. The divider

is configured using GLOBAL_CLK_CFG:DIVIDED_CLK_SEL

8 = CTS. Output High when clear to send a new command, output low otherwise.

9 = INV_CTS. Output low when clear to send a new command, output high otherwise.

10 = Output low unless command overlap occurs. When command overlap occurs output goes high until the rising

edge of CTS.

11 = SPI. Serial data out.

12 = Output low until power on reset is complete then output high.

13 = Output low normally. Pulses high when calibration timer expires. To use the calibration timer, the 32 kHz clock

must be enabled. Calibration timer period is configured using GLOBAL_WUT_CONFIG:WUT_CAL_PERIOD

and enabled by GLOBAL_WUT_CONFIG:CAL_EN.

14 = Output low normally. Pulses high when wakeup timer expires. To use the wakeup timer the 32 kHz clock must

be enabled. The wut period is configured using GLOBAL_WUT_M_15_8, GLOBAL_WUT_M_7_0 and

GLOBAL_WUT_R and enabled by GLOBAL_WUT_CONFIG:WUT_EN.

15 = Unused0

16 = TX data CLK output to be used in conjuction with TX Data pin.

17 = RX data CLK output to be used in conjuction with RX Data pin.

18 = unused1

19 = TX data. This option is not to be used for Tx direct mode input. For Tx direct mode input, use option 4..

20 = RX data.

21 = RX raw data.

22 = Antenna 1 Switch used for antenna diversity.

23 = Antenna 2 Switch used for antenna diversity.

24 = High when a valid preamble is detected. Returns to output low after a packet is received or sync word timeout

occurs.

25 = High when an invalid preamble is detected. Output low normally. Pulses output high when the preamble is not

detected within a period of time (determined by PREAMBLE_CONFIG_STD_2:RX_PREAMBLE_TIMEOUT)

after the demodulator is enabled.

26 = High when a sync word is detected. Returns to output low after the packet is received.

27 = High when RSSI above clear channel assesment threshold, low when below threshold. Threshold set by

MODEM_RSSI_THRESH.

32 = High while in the transmit state.

33 = High while in the receive state.

34 = High while the rx fifo is almost full.

35 = High while the tx fifo is almost empty.

36 = High while the battery voltage is low.

37 = High when RSSI above clear channel assesment threshold. Goes low on sync detect or exiting rx state.

38 = Toggles when hop occurs.

39 = Toggles when the hop table wraps.

GPIO1_PULL_CTL

0 = Disable pullup. Recommended setting if pin is driven.

1 = Enable pullup.

GPIO1_MODE[5:0]

0 = Do not modify the behavior of this pin.

1 = Input and output drivers disabled.

2 = CMOS output driven low.

3 = CMOS output driven high.

4 = CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g. TX Direct Mode Data In).

The actual function of this pin is controlled by other properties.

5 = 32 kHz clock. Outputs 32 kHz clock selected using GLOBAL_CLK_CFG:CLK_32K_SEL. Output low if the

32 kHz clock is not enabled.

AN625

18 Rev. 0.1

6 = BOOT_CLK. Outputs boot clock. This will only output when the device is in SPI ACTIVE state because that is the

only time the boot clock is active.

7 = Divided MCU clock. Outputs divided clock. Output divided boot clock in SPI ACTIVE state, Output low while in

SLEEP state as the divided clock source is not running, and Output divided XTAL in all other states. The divider

is configured using GLOBAL_CLK_CFG:DIVIDED_CLK_SEL

8 = CTS. Output High when clear to send a new command, output low otherwise.

9 = INV_CTS. Output low when clear to send a new command, output high otherwise.

10 = Output low unless command overlap occurs. When command overlap occurs output goes high until the rising

edge of CTS.

11 = SPI. Serial data out.

12 = Output low until power on reset is complete then output high.

13 = Output low normally. Pulses high when calibration timer expires. To use the calibration timer, the 32 kHz clock

must be enabled. Calibration timer period is configured using GLOBAL_WUT_CONFIG:WUT_CAL_PERIOD

and enabled by GLOBAL_WUT_CONFIG:CAL_EN.

14 = Output low normally. Pulses high when wakeup timer expires. To use the wakeup timer the 32 kHz clock must

be enabled. The wut period is configured using GLOBAL_WUT_M_15_8, GLOBAL_WUT_M_7_0 and

GLOBAL_WUT_R and enabled by GLOBAL_WUT_CONFIG:WUT_EN.

15 = unused0

16 = TX data CLK output to be used in conjuction with TX Data pin.

17 = RX data CLK output to be used in conjuction with RX Data pin.

18 = unused1

19 = TX data. This option is not to be used for Tx direct mode input. For Tx direct mode input, use option 4.

20 = RX data.

21 = RX raw data.

22 = Antenna 1 Switch used for antenna diversity.

23 = Antenna 2 Switch used for antenna diversity.

24 = High when a valid preamble is detected. Returns to output low after a packet is received or sync word timeout

occurs.

25 = High when an invalid preamble is detected. Output low normally. Pulses output high when the preamble is not

detected within a period of time (determined by PREAMBLE_CONFIG_STD_2:RX_PREAMBLE_TIMEOUT)

after the demodulator is enabled.

26 = High when a sync word is detected. Returns to output low after the packet is received.

27 = High when RSSI above clear channel assesment threshold, low when below threshold. Threshold set by

MODEM_RSSI_THRESH.

32 = High while in the transmit state.

33 = High while in the receive state.

34 = High while the rx fifo is almost full.

35 = High while the tx fifo is almost empty.

36 = High while the battery voltage is low.

37 = High when RSSI above clear channel assesment threshold. Goes low on sync detect or exiting rx state.

38 = Toggles when hop occurs.

39 = Toggles when the hop table wraps.

GPIO2_PULL_CTL

0 = Disable pullup. Recommended setting if pin is driven.

1 = Enable pullup.

GPIO2_MODE[5:0]

0 = Do not modify the behavior of this pin.

1 = Input and output drivers disabled.

2 = CMOS output driven low.

3 = CMOS output driven high.

4 = CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g. TX Direct Mode Data In).

The actual function of this pin is controlled by other properties.

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Rev. 0.1 19

5 = 32 kHz clock. Outputs 32 kHz clock selected using GLOBAL_CLK_CFG:CLK_32K_SEL. Output low if the

32 kHz clock is not enabled.

6 = BOOT_CLK. Outputs boot clock. This will only output when the device is in SPI ACTIVE state because that is the

only time the boot clock is active.

7 = Divided MCU clock. Outputs divided clock. Output divided boot clock in SPI ACTIVE state, Output low while in

SLEEP state as the divided clock source is not running, and Output divided XTAL in all other states. The divider

is configured using GLOBAL_CLK_CFG:DIVIDED_CLK_SEL

8 = CTS. Output High when clear to send a new command, output low otherwise.

9 = INV_CTS. Output low when clear to send a new command, output high otherwise.

10 = Output low unless command overlap occurs. When command overlap occurs output goes high until the rising

edge of CTS.

11 = SPI. Serial data out.

12 = Output low until power on reset is complete then output high.

13 = Output low normally. Pulses high when calibration timer expires. To use the calibration timer, the 32 kHz clock

must be enabled. Calibration timer period is configured using GLOBAL_WUT_CONFIG:WUT_CAL_PERIOD

and enabled by GLOBAL_WUT_CONFIG:CAL_EN.

14 = Output low normally. Pulses high when wakeup timer expires. To use the wakeup timer the 32 kHz clock must

be enabled. The wut period is configured using GLOBAL_WUT_M_15_8, GLOBAL_WUT_M_7_0 and

GLOBAL_WUT_R and enabled by GLOBAL_WUT_CONFIG:WUT_EN.

15 = Unused0

16 = TX data CLK output to be used in conjuction with TX Data pin.

17 = RX data CLK output to be used in conjuction with RX Data pin.

18 = unused1

19 = TX data. This option is not to be used for Tx direct mode input. For Tx direct mode input, use option 4.

20 = RX data.

21 = RX raw data.

22 = Antenna 1 Switch used for antenna diversity.

23 = Antenna 2 Switch used for antenna diversity.

24 = High when a valid preamble is detected. Returns to output low after a packet is received or sync word timeout

occurs.

25 = High when an invalid preamble is detected. Output low normally. Pulses output high when the preamble is not

detected within a period of time (determined by PREAMBLE_CONFIG_STD_2:RX_PREAMBLE_TIMEOUT)

after the demodulator is enabled.

26 = High when a sync word is detected. Returns to output low after the packet is received.

27 = High when RSSI above clear channel assesment threshold, low when below threshold. Threshold set by

MODEM_RSSI_THRESH.

32 = High while in the transmit state.

33 = High while in the receive state.

34 = High while the rx fifo is almost full.

35 = High while the tx fifo is almost empty.

36 = High while the battery voltage is low.

37 = High when RSSI above clear channel assesment threshold. Goes low on sync detect or exiting rx state.

38 = Toggles when hop occurs.

39 = Toggles when the hop table wraps.

GPIO3_PULL_CTL

0 = Disable pullup. Recommended setting if pin is driven.

1 = Enable pullup.

GPIO3_MODE[5:0]

0 = Do not modify the behavior of this pin.

1 = Input and output drivers disabled.

2 = CMOS output driven low.

3 = CMOS output driven high.

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20 Rev. 0.1

4 = CMOS input. This is used for all GPIO functions that require the pin to be an input (e.g. TX Direct Mode Data In).

The actual function of this pin is controlled by other properties.

5 = 32 kHz clock. Outputs 32 kHz clock selected using GLOBAL_CLK_CFG:CLK_32K_SEL. Output low if the

32 kHz clock is not enabled.

6 = BOOT_CLK. Outputs boot clock. This will only output when the device is in SPI ACTIVE state because that is the

only time the boot clock is active.

7 = Divided MCU clock. Outputs divided clock. Output divided boot clock in SPI ACTIVE state, Output low while in

SLEEP state as the divided clock source is not running, and Output divided XTAL in all other states. The divider

is configured using GLOBAL_CLK_CFG:DIVIDED_CLK_SEL

8 = CTS. Output High when clear to send a new command, output low otherwise.

9 = INV_CTS. Output low when clear to send a new command, output high otherwise.

10 = Output low unless command overlap occurs. When command overlap occurs output goes high until the rising

edge of CTS.

11 = SPI. Serial data out.

12 = Output low until power on reset is complete then output high.

13 = Output low normally. Pulses high when calibration timer expires. To use the calibration timer, the 32 kHz clock

must be enabled. Calibration timer period is configured using GLOBAL_WUT_CONFIG:WUT_CAL_PERIOD

and enabled by GLOBAL_WUT_CONFIG:CAL_EN.

14 = Output low normally. Pulses high when wakeup timer expires. To use the wakeup timer the 32 kHz clock must

be enabled. The wut period is configured using GLOBAL_WUT_M_15_8, GLOBAL_WUT_M_7_0 and

GLOBAL_WUT_R and enabled by GLOBAL_WUT_CONFIG:WUT_EN.

15 = unused0

16 = TX data CLK output to be used in conjuction with TX Data pin.

17 = RX data CLK output to be used in conjuction with RX Data pin.

18 = unused1

19 = TX data. This option is not to be used for Tx direct mode input. For Tx direct mode input, use option 4.

20 = RX data.

21 = RX raw data.

22 = Antenna 1 Switch used for antenna diversity.

23 = Antenna 2 Switch used for antenna diversity.

24 = High when a valid preamble is detected. Returns to output low after a packet is received or sync word timeout

occurs.

25 = High when an invalid preamble is detected. Output low normally. Pulses output high when the preamble is not

detected within a period of time (determined by PREAMBLE_CONFIG_STD_2:RX_PREAMBLE_TIMEOUT)

after the demodulator is enabled.

26 = High when a sync word is detected. Returns to output low after the packet is received.

27 = High when RSSI above clear channel assesment threshold, low when below threshold. Threshold set by

MODEM_RSSI_THRESH.

32 = High while in the transmit state.

33 = High while in the receive state.

34 = High while the rx fifo is almost full.

35 = High while the tx fifo is almost empty.

36 = High while the battery voltage is low.

37 = High when RSSI above clear channel assesment threshold. Goes low on sync detect or exiting rx state.

38 = Toggles when hop occurs.

39 = Toggles when the hop table wraps.

NIRQ_DRV_PULL

0 = Disable pullup. Recommended setting if pin is driven.

1 = Enable pullup.

NIRQ_MODE[5:0]

0 = Do not modify the behavior of this pin.

1 = Input and output drivers disabled.

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