VLSI测试原理与架构解析

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"VLSI测试原理与架构" 集成电路测试是电子工程领域中至关重要的一环，尤其是在VLSI（Very Large Scale Integration，超大规模集成电路）技术迅速发展的今天。VLSI测试涉及对集成度极高的芯片进行功能验证和缺陷检测，确保它们在实际应用中的可靠性。《VLSI测试原理与架构》作为一本该领域的经典著作，全面地阐述了这一主题，旨在帮助电子设计师应对设计、自动化、制造和测试中的系统化挑战。随着硅技术的进步和应用场景的多样化，电子设计师需要采用系统化的视角来设计电路。这带来了设计方法学、设计自动化、制造工艺以及测试策略的新问题。《摩根·考夫曼系统硅系列》正是为了回应这些挑战而设立的出版系列，由业界权威专家撰写，他们能够深入探讨并提供解决方案。书中可能会涵盖的内容可能包括： 1. VLSI测试的基础：介绍测试的基本概念，如测试向量、故障模型和测试生成算法，这些都是确保集成电路正常运行的关键步骤。 2. 测试架构：讨论不同类型的测试架构，如边界扫描、片上测试（On-Chip Testing）和系统级测试，以及它们如何在复杂的VLSI设计中实现有效的故障检测。 3. 缺陷分析：分析集成电路制造过程中的常见缺陷，如短路、开路、多晶硅桥接等，并探讨如何通过测试来识别和定位这些问题。 4. 测试自动化：探讨如何利用高级设计语言（如VHDL和SystemVerilog）以及自动化工具来提高测试效率，减少设计周期。 5. 系统级测试：在系统层面考虑测试，包括嵌入式系统和SoC（System on Chip）的测试策略，这涉及到软硬件协同设计和验证。 6. 组件建模：在ASIC和FPGA验证中，组件模型扮演着重要角色，书中可能会详细讲解如何建立这些模型以进行有效的功能验证。 7. 多处理器SoC测试：对于包含多个处理单元的复杂系统，测试策略会更加复杂，可能涉及多线程同步、通信协议验证和功耗管理等问题。 8. 性能评估与优化：如何通过测试来评估系统的性能，并根据结果进行优化，以提高整体系统效能。《VLSI测试原理与架构》不仅提供了丰富的理论知识，还强调了实践应用，为电子工程师提供了全面理解VLSI测试的工具和方法，是该领域的工程师和研究人员不可或缺的参考书目。

Elsevier US Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page: xvii

Contents xvii

10 Boundary Scan and Core-Based Testing 557

Kuen-Jong Lee

10.1 Introduction ................................558

10.1.1 IEEE 1149 Standard Family ..................558

10.1.2 Core-Based Design and Test Considerations .........559

10.2 Digital Boundary Scan (IEEE Std. 1149.1) ..............561

10.2.1 Basic Concept ..........................561

10.2.2 Overall 1149.1 Test Architecture and Operations ......562

10.2.3 Test Access Port and Bus Protocols ..............564

10.2.4 Data Registers and Boundary-Scan Cells ..........565

10.2.5 TAP Controller ..........................567

10.2.6 Instruction Register and Instruction Set ...........569

10.2.7 Boundary-Scan Description Language ............574

10.2.8 On-Chip Test Support with Boundary Scan .........574

10.2.9 Board and System-Level Boundary-Scan Control

Architectures ...........................576

10.3 Boundary Scan for Advanced Networks (IEEE 1149.6) .......579

10.3.1 Rationale for 1149.6 .......................579

10.3.2 1149.6 Analog Test Receiver ..................581

10.3.3 1149.6 Digital Driver Logic ...................581

10.3.4 1149.6 Digital Receiver Logic .................582

10.3.5 1149.6 Test Access Port (TAP) .................584

10.3.6 Summary .............................585

10.4 Embedded Core Test Standard (IEEE Std. 1500) ..........585

10.4.1 SOC (System-on-Chip) Test Problems ............585

10.4.2 Overall Architecture .......................587

10.4.3 Wrapper Components and Functions .............589

10.4.4 Instruction Set ..........................597

10.4.5 Core Test Language (CTL) ...................601

10.4.6 Core Test Supporting and System Test Configurations . . 603

10.4.7 Hierarchical Test Control and Plug-and-Play ........606

10.5 Comparisons between the 1500 and 1149.1 Standards .......610

10.6 Concluding Remarks ...........................611

10.7 Exercises ..................................612

Acknowledgments .................................614

References .....................................614

11 Analog and Mixed-Signal Testing 619

Chauchin Su

11.1 Introduction ................................619

11.1.1 Analog Circuit Properties ....................620

11.1.1.1 Continuous Signals .................621

Elsevier US Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page: xviii

xviii Contents

11.1.1.2 Large Range of Circuits ..............621

11.1.1.3 Nonlinear Characteristics .............621

11.1.1.4 Feedback Ambiguity ................622

11.1.1.5 Complicated Cause–Effect Relationship .....622

11.1.1.6 Absence of Suitable Fault Model .........622

11.1.1.7 Requirement for Accurate Instruments for

Measuring Analog Signals .............623

11.1.2 Analog Defect Mechanisms and Fault Models ........623

11.1.2.1 Hard Faults ......................625

11.1.2.2 Soft Faults ......................625

11.2 Analog Circuit Testing ..........................627

11.2.1 Analog Test Approaches ....................627

11.2.2 Analog Test Waveforms .....................629

11.2.3 DC Parametric Testing .....................631

11.2.3.1 Open-Loop Gain Measurement ..........632

11.2.3.2 Unit Gain Bandwidth Measurement .......633

11.2.3.3 Common Mode Rejection Ratio Measurement . 634

11.2.3.4 Power Supply Rejection Ratio Measurement . . 635

11.2.4 AC Parametric Testing .....................635

11.2.4.1 Maximal Output Amplitude Measurement ....636

11.2.4.2 Frequency Response Measurement ........637

11.2.4.3 SNR and Distortion Measurement ........639

11.2.4.4 Intermodulation Distortion Measurement ....641

11.3 Mixed-Signal Testing ...........................641

11.3.1 Introduction to Analog–Digital Conversion .........642

11.3.2 ADC and DAC Circuit Structure ................644

11.3.2.1 DAC Circuit Structure ...............646

11.3.2.2 ADC Circuit Structure ...............646

11.3.3 ADC/DAC Specification and Fault Models ..........647

11.3.4 IEEE 1057 Standard ......................652

11.3.5 Time-Domain ADC Testing ...................654

11.3.5.1 Code Bins .......................654

11.3.5.2 Code Transition Level Test (Static) ........655

11.3.5.3 Code Transition Level Test (Dynamic) ......655

11.3.5.4 Gain and Offset Test ................656

11.3.5.5 Linearity Error and Maximal Static Error ....657

11.3.5.6 Sine Wave Curve-Fit Test ..............658

11.3.6 Frequency-Domain ADC Testing ...............658

11.4 IEEE 1149.4 Standard for a Mixed-Signal Test Bus .........658

11.4.1 IEEE 1149.4 Overview .....................659

11.4.1.1 Scope of the Standard ...............660

11.4.2 IEEE 1149.4 Circuit Structures ................661

11.4.3 IEEE 1149.4 Instructions ...................665

11.4.3.1 Mandatory Instructions ..............665

11.4.3.2 Optional Instructions ................665

Elsevier US Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page: xix

Contents xix

11.4.4 IEEE 1149.4 Test Modes ....................666

11.4.4.1 Open/Short Interconnect Testing .........666

11.4.4.2 Extended Interconnect Measurement ......667

11.4.4.3 Complex Network Measurement .........671

11.4.4.4 High-Performance Configuration .........672

11.5 Concluding Remarks ...........................673

11.6 Exercises ..................................673

Acknowledgments .................................676

References .....................................677

12 Test Technology Trends in the Nanometer Age 679

Kwang-Ting (Tim) Cheng, Wen-Ben Jone, and Laung-Terng (L.-T.) Wang

12.1 Test Technology Roadmap ........................680

12.2 Delay Testing ...............................685

12.2.1 Test Application Schemes for Testing Delay Defects ....686

12.2.2 Delay Fault Models .......................687

12.2.3 Summary .............................690

12.3 Coping with Physical Failures, Soft Errors,

and Reliability Issues ...........................692

12.3.1 Signal Integrity and Power Supply Noise ..........692

12.3.1.1 Integrity Loss Fault Model .............693

12.3.1.2 Location .......................694

12.3.1.3 Pattern Generation .................694

12.3.1.4 Sensing and Readout ................695

12.3.2 Parametric Defects, Process Variations, and Yield .....696

12.3.2.1 Defect-Based Test ..................697

12.3.3 Soft Errors ............................698

12.3.4 Fault Tolerance .........................701

12.3.5 Defect and Error Tolerance ..................705

12.4 FPGA Testing ...............................706

12.4.1 Impact of Programmability ..................706

12.4.2 Testing Approaches .......................708

12.4.3 Built-In Self-Test of Logic Resources .............708

12.4.4 Built-In Self-Test of Routing Resources ...........709

12.4.5 Recent Trends ..........................710

12.5 MEMS Testing ...............................711

12.5.1 Basic Concepts for Capacitive MEMS Devices .......711

12.5.2 MEMS Built-In Self-Test ....................713

12.5.2.1 Sensitivity BIST Scheme ..............713

12.5.2.2 Symmetry BIST Scheme ..............713

12.5.2.3 A Dual-Mode BIST Technique ...........714

12.5.3 A BIST Example for MEMS Comb Accelerometers ....716

12.5.4 Conclusions ...........................719

Elsevier US Jobcode:0wtp-Prelims 1-6-2006 4:22p.m. Page: xxi

PREFACE

Beginning with the introduction of commercial manufacturing of integrated circuits

(ICs) in the early 1960s, modern electronics testing has a history of more than 40

years. The integrated circuit was developed in 1958, concurrently at Texas Instru-

ments (TI) and Fairchild Semiconductor. Today, semiconductors lie at the heart of

ongoing advances across the electronics industry. The industry enjoyed a banner

year in 2005, with almost $230 billion in sales worldwide.

The introduction of new technologies, especially nanometer technologies with

90 nm or smaller geometry, has allowed the semiconductor industry to keep pace

with increased performance-capacity demands from consumers. This has bright-

ened the prospects for future industry growth; however, new technologies come

with new challenges. Semiconductor test costs have been growing steadily. Test

costs can now amount to 40% of overall product cost. In addition, product quality

and yield could drop significantly if these chips are not designed for testability and

thoroughly tested.

New problems encountered in semiconductor testing are being recognized

quickly today. Because very-large-scale integration (VLSI) technologies drive test

technologies, more effective test technologies are key to success in today’s compet-

itive marketplace. It is recognized that, in order to tackle the problems associated

with testing semiconductor devices, it is necessary to attack them at earlier design

stages. The field of design for testability (DFT) is a mature one today. Test cost

can be significantly reduced by inserting DFT in earlier design stages; thus, it is

important to expose students and practitioners to the most recent, yet fundamen-

tal, VLSI test principles and DFT architectures in an effort to help them design

better quality products now and in the future that can be reliably manufactured in

quantity.

In this context, it is important to make sure that undergraduates and practition-

ers, in addition to graduate students and researchers, are introduced to the variety

of problems encountered in semiconductor testing and that they are made aware

of the new methods being developed to solve these problems at earlier stages of

design. A very important factor in doing so is to ensure that introductory textbooks

for semiconductor testing are kept up to date with the latest process, design, and

test technology advances.

This textbook is being made available with this goal in mind. It is a fundamental

yet comprehensive guide to new DFT methods that will show readers how to design

a testable and quality product, drive down test cost, improve product quality and

yield, and speed up time-to-market and time-to-volume. Intended users of the book

include undergraduates, engineers and engineering managers who have the need

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