TI ADS7128 8通道12位ADC：I2C接口与GPIO功能

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"TI-ADS7128.pdf" TI公司的ADS7128是一款小巧的8通道12位模数转换器（ADC），它具备I2C接口、通用输入/输出（GPIO）功能以及CRC校验，适用于各种信号处理应用。这款器件的主要特点包括其紧凑的封装尺寸（3mm x 3mm WQFN）、高度灵活的通道配置、模拟监控功能、宽泛的工作电源电压范围以及内置的安全保护机制。 1. 小型封装：ADS7128采用3mm x 3mm的小型WQFN封装，适合空间有限的设计。 2. 通道配置：该设备的8个通道可以被配置为模拟输入、数字输入或数字输出，最多可支持8个输入或输出。 3. GPIO扩展：GPIO引脚支持开漏和推挽数字输出，可用于扩展系统I/O功能。 4. 模拟监控：每个通道都有可编程的高低阈值，能实现精确的模拟信号监控，并且具有事件计数器功能，用于瞬态抑制。 5. 工作电压范围：AVDD电源电压范围为2.35V到5.5V，DVDD电源电压范围为1.65V到5.5V，适应性强。 6. 温度范围：能够在-40°C到+85°C的温度范围内稳定工作，确保了在各种环境条件下的可靠性。 7. CRC功能：提供了数据读取/写入的CRC校验，以及上电配置CRC，增强了数据传输的准确性。 8. I2C接口：支持标准的I2C通信协议，便于与微控制器等其他设备进行通信。此外，ADS7128还包含了一些高级特性，如数字窗口比较器、可编程平均滤波器、均方根（RMS）模块和零跨导（ZCD）模块。这些模块可以提升信号质量，降低噪声，以及对输入信号进行实时计算。ADC内部集成了多路复用器，允许用户选择不同的输入通道进行采样。VCC、AVDD和GND引脚负责供电和接地，而ADDR引脚则用于设置I2C接口的设备地址。 OVP（过压保护）和OCP（过流保护）功能是ADS7128的另一大亮点，它们可以保护设备免受过高电压或电流的损害。LOAD引脚可能用于控制ADC的采样速率或数据读取，而ALERT引脚可以提供故障指示。 TI的ADS7128是一款功能强大的8通道ADC，适合需要高精度、低功耗和小型化解决方案的工业、汽车和医疗应用。设计时应参照最新的英文数据手册以获取最准确的技术信息。

ADVANCEINFORMATION

ADS7128

ZHCSJS7 –MAY 2019

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8.3.9 Oscillator and Timing Control

The device uses an internal oscillator for conversions. When using the averaging module or the RMS module,

the host initiates the first conversion and all subsequent conversions are generated internally by the device.

However, in the autonomous mode of operation, the start of the conversion signal is generated by the device. 表

5 shows that when the device generates the start of the conversion, the sampling rate is controlled by the

OSC_SEL and CLK_DIV[3:0] register fields.

表表 5. Configuring Sampling Rate for Internal Conversion Start Control

CLK_DIV[3:0]

OSC_SEL = 0 OSC_SEL = 1

SAMPLING FREQUENCY,

CYCLE

(kSPS)

CYCLE TIME,

CYCLE

(µs)

SAMPLING FREQUENCY, f

CYCLE

(kSPS)

CYCLE TIME, t

CYCLE

(µs)

0000b 1000 1 31.25 32

0001b 666.7 1.5 20.83 48

0010b 500 2 15.63 64

0011b 333.3 3 10.42 96

0100b 250 4 7.81 128

0101b 166.7 6 5.21 192

0110b 125 8 3.91 256

0111b 83 12 2.60 384

1000b 62.5 16 1.95 512

1001b 41.7 24 1.3 768

1010b 31.3 32 0.98 1024

1011b 20.8 48 0.65 1536

1100b 15.6 64 0.49 2048

1101b 10.4 96 0.33 3072

The conversion time of the device (see t

CONV

in the Switching Characteristics table) is independent of the

OSC_SEL and CLK_DIV[3:0] configuration.

8.3.10 Output Data Format

图 6 illustrates various I

C frames for reading data.

• Read the ADC conversion result: Two 8-bit I

C packets are required (frame A).

• Read the averaged conversion result: Two 8-bit I

C packets are required (frame B).

• Read data with the channel ID or status flags appended: The 4-bit channel ID or status flags can be

appended to the 12-bit ADC result by configuring the APPEND_STATUS field in the GENERAL_CFG

by the digital window comparator. When the channel ID or status flags are appended to the 12-bit ADC data,

two I

C packets are required (frame C). If the channel ID or status flags are appended to the 16-bit average

result, three I

C frames are required (frame D).

ADVANCEINFORMATION

ALERT_CH_SEL[7]

EVENT_RGN[7]

ADC

Averager

1 to 128

12-bit ADC data

[15:4] Average result

High threshold -

Hysteresis

Event

Counter

EVENT_HIGH_FLAG

EVENT_LOW_FLAG

Low threshold +

Hysteresis

ALERT_CH_SEL[0]

All registers are specific for

individual analog input channels

ALERT

EVENT_RGN[0]

MUX

Digital input CH0

PIN_CFG

D11 D10 D9 D8 D7 D6 D5 D4 A D3 D2 D1 D0 A

D11 D10 D9 D8 D7 D6 D5 D4A AD3 D2 D1 D0D12D13D14D15

D11 D10 D9 D8 D7 D6 D5 D4 A D3 D2 D1 D0 0 0 0 0 A

4-bit Channel ID

or Status Flags

S 7-bit Slave Address R A

Sample A

Clock stretching for conversion time

Sample A + 1

Frame A : Reading ADC data

Frame C : Reading ADC data with status flags or channel ID appended

Frame B : Reading ADC data with averaging enabled

D8 D7 D6AD14D15S 7-bit Slave Address R A D0 A A

4-bit Channel ID

or Status Flags

0 0 0 0

Frame D : Reading ADC data with averaging enabled &

status flags or channel ID appended

Data from host to device Data from device to host

ADS7128

www.ti.com.cn

ZHCSJS7 –MAY 2019

图图 6. Data Frames for Reading Data

When status flags are enabled, APPEND_STATUS is set to 10b and four bits are appended to the ADC output.

The device outputs status flags in this order: {1b, 0b, CRCERR_IN, ALERT}. The level transitions on the digital

interface, resulting from the fixed 1b and 0b in the status flags, can be used to detect if the digital outputs are

shorted to a fixed voltage in the system. The CRCERR_IN flag reflects the corresponding bit in the

GENERAL_CFG register. The ALERT flag is the output of the logical OR of the bits in the EVENT_FLAG

8.3.11 Digital Window Comparator

The internal digital window comparator (DWC) is available in all functional modes of the device (see the Device

Functional Modes section for details). The digital window comparator controls output of the ALERT pin buffer.

The ALERT pin can be configured as open-drain (default) or push-pull output using the ALERT_DRIVE bit in the

ALERT_PIN_CFG register. 图 7 shows a block diagram for the digital window comparator.

图图 7. Digital Window Comparator Block Diagram

ADVANCEINFORMATION

0x000

0xFFF

Digital code

Samples

High threshold -

Hysteresis

Low threshold +

Hysteresis

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Signal above limit

0x000

0xFFF

Digital code

Samples

High threshold -

Hysteresis

Low threshold +

Hysteresis

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Signal below limit

0x000

0xFFF

Digital code

Samples

High threshold -

Hysteresis

Low threshold +

Hysteresis

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Signal out of band

0x000

0xFFF

Digital code

Samples

High threshold -

Hysteresis

Low threshold +

Hysteresis

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Signal in band

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Signal out of band

DWC_CH_POL = 0

DWC_CH_POL = 1

ADS7128

ZHCSJS7 –MAY 2019

www.ti.com.cn

The low-side threshold, high-side threshold, event counter, and hysteresis parameters are independently

programmable for each input channel. 图 8 shows the events that can be monitored for every analog input

channel by the window comparator.

图图 8. Event Monitoring With the Window Comparator

To enable the digital window comparator, set the DWC_EN bit in the GENERAL_CFG register. By default,

hysteresis is 0, the high threshold is 0xFFF, and the low threshold is 0x000. A 12-bit straight binary code cannot

be higher than 0xFFF or lower than 0x000, thus the thresholds have no effect unless set to different values. 图 8

shows the various types of event that can be detected by adjusting the thresholds. For detecting when a signal is

in-band, the EVENT_RGN register must be configured. In each of the cases shown in 图 8, either or both

EVENT_HIGH_FLAG and EVENT_LOW_FLAG can be set.

The programmable event counter counts consecutive thresholds violations before alert flags can be set. The

event count can be set to a higher value to avoid transients in the input signal setting the alert flags.

In order to assert the ALERT pin when the alert flag is set for a particular analog input channel, set the

corresponding bit in the ALERT_CH_SEL register. Alert flags are set regardless of the ALERT_CH_SEL

configuration if DWC_EN is 1 and the high or low thresholds are exceeded.

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