ST25R3911B：高性能NFC读卡器，支持远距离传输

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"ST25R3911B是一款高性能的NFC发起器/高频读卡器集成电路，适用于远距离NFC传输，支持高达10cm的非接触场景。该芯片集成了模拟前端（AFE）和高度集成的数据帧系统，符合ISO18092（NFCIP-1）发起者、ISO14443A、ISO14443B、ISO15693和FeliCa™标准。此外，它还支持VHBR（3.4Mbit/s PICC到PCD帧，6.8Mbit/s AFE和PCD到PICC帧），并具有电容感应唤醒功能。" ST25R3911B的主要特性包括： 1. 支持多种NFC和RFID标准：该芯片兼容ISO18092（NFCIP-1）主动P2P模式，以及ISO14443A、ISO14443B、ISO15693和FeliCa™协议，能够处理各种NFC和RFID通信需求。 2. 高速通信：支持VHBR（Very High Bit Rate）技术，提供3.4Mbit/s和6.8Mbit/s的数据传输速率，显著提高了通信效率。 3. 电容感应唤醒：具备电容感应功能，可以在设备待机时通过感应周围环境的变化来唤醒系统，节省能源。 4. 自动调谐和调制指数调整：内置自动天线调谐系统，优化天线LC谐振电路，同时能自动调整调制指数，确保通信质量。 5. 多模式解调器：包括AM和PM解调通道，可自动选择，适应不同的通信条件。 6. 动态功率输出（DPO）：根据通信需求动态调整输出功率，最高可达1.4W（差分输出）。 7. 自适应增益控制：用户可选和自动增益控制，确保信号强度适中，防止过载或失真。 8. 透明和流模式：支持MIFARE™ Classic兼容协议和其他自定义协议的实施。 9. 双天线驱动：单端模式下可以驱动两个天线，增加了设计灵活性。 10. 快速启动晶体振荡器输入：支持13.56MHz或27.12MHz晶振，快速启动工作。 11. 高速SPI接口：6Mbit/s SPI接口带有96字节的FIFO，提高数据处理速度。 12. 宽电源电压范围：2.4V至5.5V，适应不同电源条件。 13. 宽工作温度范围：-40°C至125°C，适合各种环境条件。 14. 封装形式：采用QFN32封装，尺寸为5x5mm，有湿式侧翼或晶圆级交付选项。 ST25R3911B是针对高效率、高可靠性的NFC应用而设计的集成电路，广泛应用于移动支付、智能卡读取、物联网设备、智能家居等领域，其强大的功能和灵活的配置能力使其成为NFC系统设计的理想选择。

Figure 6. Phase detector inputs and output in case of 90º phase shift

SP_A

Input 1

Input 2

Output

Figure 7. Phase detector inputs and output in case of 135º phase shift

SP_A

Input 1

Input 2

Output

Amplitude detector

Signals from pins RFI1 and RFI2 are used as inputs to the self-mixing stage. The output of this stage is a DC

voltage proportional to amplitude of signal on pins RFI1 and RFI2. During execution of direct command Measure

Amplitude this output is multiplexed to A/D converter input.

1.2.10 External field detector

The External Field Detector is used to detect the presence of an external device generating an RF field. It is

automatically switched on in NFCIP-1 active communication modes; it can also be used in other modes. The

External field detector supports two different detection thresholds, Peer Detection Threshold and Collision

Avoidance Threshold. The two thresholds can be independently set by writing the External field detector threshold

Peer detection threshold

This threshold is used to detect the field emitted by peer NFC device with whom NFC communication is going on

(initiator field in case the ST25R3911B is a target and the opposite, target field in case the ST25R3911B is an

initiator). It can be selected in the range from 75 to 800 mV

. When this threshold is enabled the External Field

Detector is in low power mode. An interrupt is generated when an external field is detected and also when it is

switched off. With such implementation it can also be used to detect the moment when the external field

disappears. This is useful to detect the moment when the peer NFC device (it can be either an initiator or a target)

has stopped emitting an RF field.

ST25R3911B

Application information

DS11793 - Rev 6

page 16/116

The External Field Detector is automatically enabled in the low power Peer Detection mode when NFCIP-1 mode

(initiator or target) is selected in the Bit rate definition register.

Additionally it can be enabled by setting bit en_fd in the Auxiliary display register.

Collision Avoidance threshold

This threshold is used during the RF Collision Avoidance sequence that is executed by sending NFC Field ON

commands (see NFC field ON commands). It can be selected in the range from 25 to 800 mV

1.2.11 Power supply system

The ST25R3911B (Figure 8) features two positive supply pins, VDD and VDD_IO.

VDD is the main power supply pin. It supplies the ST25R3911B blocks through three regulators (VSP_A, VSP_D

and VSP_RF).

range from 2.4 to 5.5 V is supported.

DD_IO

is used to define supply level for digital communication pins (/SS, MISO, MOSI, SCLK, IRQ, MCU_CLK).

Digital communication pins interface with ST25R3911B logic through level shifters, therefore the internal supply

voltage can be either higher or lower than V

DD_IO

. V

DD_IO

range from 1.65 to 5.5 V is supported.

Figure 8. ST25R3911B power supply

Power-down

support

sup3V

50 Ω

RV<3:0>

VSP_RF

REG

BGR

and

AGC

AUTOREG

VSP_A

1 kΩ

VSP_D

AGD

reg 2B

reg 2A

VSP_A

REG

VSP_D

REG

adjust

VSP_RF

VDD

Figure 8 shows the building blocks of the ST25R3911B power supply system and the signals that control it.

The power supply system contains three regulators, a power-down support block, a block generating analog

reference voltage (AGD) and a block performing automatic power supply adjustment procedure. The three

regulators are providing supply to analog blocks (VSP_A), logic (VSP_D) and transmitter (VSP_RF). The use of

VSP_A and VSP_D regulators is mandatory at 5 V power supply to provide regulated voltage to analog and logic

blocks that only use 3.3 V devices. The use of VSP_A and VSP_D regulators at 3 V supply and VSP_RF

regulator at any supply voltage is recommended to improve system PSRR.

Regulated voltage can be adjusted automatically to have maximum possible regulated voltage while still having

good PSRR. All regulator pins also have corresponding negative supply pins that are externally connected to

ground potential (VSS). The reason for separation is in decoupling of noise induced by voltage drops on the

internal power supply lines.

Figure 2 and Figure 3 show typical ST25R3911B application schematics with all regulators used. All regulator pins

and AGD voltage are buffered with capacitors. Recommended blocking capacitor values are detailed in Table 4.

Table 4. Recommended blocking capacitor values

Pins

Recommended capacitors

AGD-VSS 1 μF, in parallel with 10 nF

ST25R3911B

Application information

DS11793 - Rev 6

page 17/116

Pins Recommended capacitors

VSP_A-VSN_A 2.2 μF, in parallel with 10 nF

VSP_D-VSN_D 2.2 μF, in parallel with 10 nF

VSP_RF-VSN_RF 2.2 μF, in parallel with 10 nF

Regulators have two basic operation modes depending on supply voltage, 3.3 V supply mode (max 3.6 V) and 5

V supply mode (max 5.5 V). The supply mode is set by writing bit sup3 V in the IO configuration register 2. Default

setting is 5 V, hence this bit has to be set to 1 after power-up in case of 3.3 V supply.

In 3.3 V mode all regulators are set to the same regulated voltage in range from 2.4 V to 3.4 V, while in 5 V only

the VSP_RF can be set in range from 3.9 V to 5.1 V, while VSP_A and VSP_D are fixed to 3.4 V.

The regulators are operating when signal en is high (en is configuration bit in Operation control register. When

signal en is low the ST25R3911B is in low power Power-down mode. In this mode consumption of the power

supply system is also minimized.

VSP_RF regulator

The intention of this regulator is to improve PSRR of the transmitter (the noise of the transmitter power supply is

emitted and fed back to the receiver). The VSP_RF regulator operation is controlled and observed by writing and

reading two regulator registers:

• Regulator voltage control register controls the regulator mode and regulated voltage. Bit reg_s controls

regulator mode. In case it is set to 0 (default state) the regulated voltage is set using direct command Adjust

Regulators. When bit reg_s is asserted to 1 regulated voltage is defined by bits rege_3 to rege_1 of the

same register. The regulated voltage adjustment range depends on the power supply mode. In case of 5 V

supply mode the adjustment range is between 3.9 V and 5.1 V in steps of 120 mV, in case of 3.3 V supply

mode the adjustment range is from 2.4 V to 3.4 V with steps of 100 mV. Default regulated voltage is the

maximum one (5.1 V and 3.4 V in case of 5 V and 3.3 V supply mode respectively).

• Regulator and Timer Display register is a read only register that displays actual regulated voltage when

regulator is operating. It is especially useful in case of automatic mode, since the actual regulated voltage,

which is the result of direct command Adjust Regulators, can be observed.

The VSP_RF regulator also includes a current limiter that limits the regulator typically to current of 200 mA

rms

normal operation (500 mA in case of short). In case the transmitter output current higher the 200 mA

rms

required, VSP_RF regulator cannot be used to supply the transmitter, VSP_RF has to be externally connected to

VDD (connection of VSP_RF to supply voltage higher than V

is not allowed).

The voltage drop of the transmitter current is the main source of the ST25R3911B power dissipation. This voltage

drop is composed of drop in the transmitter driver and in the drop on VSP_RF regulator. Due to this it is

recommended to set regulated voltage using direct command Adjust Regulators. It results in good power supply

rejection ration with relatively low dissipated power due to regulator voltage drop.

In power‑down mode the VSP_RF regulator is not operating.

VSP_RF pin is connected to VDD through 1 kΩ resistor.

Connection through resistors ensures smooth power-up of the system and a smooth transition from power‑down

mode to other operating modes.

VSP_A and VSP_D regulators

VSP_A and VSP_D regulators are used to supply the ST25R3911B analog and digital blocks, respectively.

In 3.3 V mode, VSP_A and VSP_D regulator are set to the same regulated voltage as the VSP_RF regulator, in 5

V mode VSP_A and VSP_D regulated voltage is fixed to 3.4 V.

The use of VSP_A and VSP_D regulators is obligatory in 5 V mode since analog and digital blocks supplied with

these two pins contain low voltage transistors that support maximum supply voltage of 3.6 V. In 3.3 V supply

mode the use of regulators is strongly recommended in order to improve PSRR of analog processing.

For low cost applications it is possible to disable the VSP_D regulator and to supply digital blocks through

external short between VSP_A and VSP_D (configuration bit vspd_off in the I/O Configuration register 2. In case

VSP_D regulator is disabled VSP_D can alternatively be supplied from VDD (in 3.3 V mode only) in case VSP_A

is not more than 300 mV lower than VDD.

ST25R3911B

Application information

DS11793 - Rev 6

page 18/116

Power-down support block

In the Power-down mode the regulators are disabled in order to save current. In this mode a low power

power‑down support block that maintains the VSP_D and VSP_A in below 3.6 V is enabled. Typical regulated

voltage in this mode is 3.1 V at 5 V supply and 2.2 V at 3 V supply. When 3.3 V supply mode is set the Power-

down support block is disabled, its output is connected to VDD through 1 kΩ resistor.

Typical consumption of Power-down support block is 600 nA at 5 V supply.

Measurement of supply voltages

Using direct command Measure Power Supply it is possible to measure V

and regulated voltages VSP_A,

VSP_D, and VSP_RF.

1.2.12 Communication with an external microcontroller

The ST25R3911B is a slave device and the external microcontroller initiates all communication. Communication is

performed by a 4-wire Serial Peripheral Interface (SPI). The ST25R3911B sends an interrupt request (pin IRQ) to

the microcontroller, which can use clock signal available on pin MCU_CLK when the oscillator is running.

Serial Peripheral Interface (SPI)

While signal /SS is high the SPI interface is in reset, while it is low the SPI is enabled. It is recommended to

keep /SS high whenever the SPI is not in use. MOSI is sampled at the falling edge of SCLK. All communication is

done in blocks of 8 bits (bytes). First two bits of first byte transmitted after high to low transition of /SS define SPI

operation mode.

Table 5. Serial data interface (4-wire interface) signal lines

Name Signal Signal level Description

/SS Digital input

CMOS

SPI Enable (active low)

MOSI Digital input Serial data input

MISO Digital output with tristate Serial data output

SCLK Digital input Clock for serial communication

MSB bit is always transmitted first (valid for address and data).

Read and Write modes support address auto-incrementing. This means that if some additional data bytes are

sent/read after the address and first data byte, they are written to/read from addresses incremented by ‘1’.

Figure 9 defines possible modes.

ST25R3911B

Application information

DS11793 - Rev 6

page 19/116

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