"STM32U575/585参考手册：应用开发完全指南"

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The STM32U575/585 reference manual, revision 21/30, published in September 2021, is a comprehensive guide designed for application developers working with the STM32U575/585 microcontrollers. This manual offers detailed and complete information on the usage of memory and peripherals for these Arm®-based 32-bit MCUs. The manual provides essential information for developers, including ordering details, mechanical and electrical device characteristics, and references to corresponding datasheets for further technical specifications. In addition to the information specific to the STM32U575/585 microcontrollers, the manual directs readers to Arm® Technical Reference Manuals for in-depth details on the Arm® Cortex®-Mx cores. These reference manuals are accessible on http://, providing developers with comprehensive resources for understanding and utilizing the core technology of these MCUs. Overall, the STM32U575/585 reference manual is an indispensable tool for developers seeking to leverage the capabilities of these advanced microcontrollers. It equips them with the knowledge and guidance necessary to effectively utilize the memory and peripherals of the STM32U575/585 MCUs, ultimately enabling the development of innovative and powerful applications. Whether it's understanding the device characteristics, ordering information, or tapping into the potential of the Arm® Cortex®-Mx cores, this reference manual serves as a crucial resource for developers looking to maximize the potential of the STM32U575/585 microcontrollers.

Contents RM0456

16/3023 RM0456 Rev 2

13.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570

13.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

13.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

13.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

13.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

13.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

13.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

13.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

13.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573

13.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

13.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 574

13.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 574

13.3.15 Using PH3 as GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574

13.3.16 OPAMPx_VINM dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

13.3.17 TrustZone security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575

13.3.18 Privileged and unprivileged modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

13.3.19 High-speed low-voltage mode (HSLV) . . . . . . . . . . . . . . . . . . . . . . . . . 576

13.3.20 I/O compensation cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576

13.4 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577

13.4.1 GPIO port mode register (GPIOx_MODER) (x = A to I) . . . . . . . . . . . . 577

13.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A to I) . . . . . . . 577

13.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A to I) . . . . 578

13.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A to I) . . . 578

13.4.5 GPIO port input data register (GPIOx_IDR) (x = A to I) . . . . . . . . . . . . 579

13.4.6 GPIO port output data register (GPIOx_ODR) (x = A to I) . . . . . . . . . . 579

13.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A to I) . . . . . . . . . 580

13.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A to I) . . . . 580

13.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A to I) . . . . . 581

13.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A to H) . . . 582

13.4.11 GPIO port bit reset register (GPIOx_BRR) (x = A to I) . . . . . . . . . . . . . 583

13.4.12 GPIO high-speed low-voltage register (GPIOx_HSLVR) (x = A to I) . . 584

13.4.13 GPIO secure configuration register (GPIOx_SECCFGR) (x = A to I) . 584

13.4.14 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585

14 Low-power general-purpose I/Os (LPGPIO) . . . . . . . . . . . . . . . . . . . . 587

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

14.2 LPGPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

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14.3 LPGPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

14.3.1 LPGPIO and GPIO configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

14.3.2 LPGPIO control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

14.3.3 LPGPIO I/O data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

14.3.4 LPGPIO I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

14.3.5 Security protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588

14.3.6 Secure clock and reset management . . . . . . . . . . . . . . . . . . . . . . . . . 588

14.4 LPGPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589

14.4.1 LPGPIO port mode register (LPGPIO_MODER) . . . . . . . . . . . . . . . . . 589

14.4.2 LPGPIO port input data register (LPGPIO_IDR) . . . . . . . . . . . . . . . . . 589

14.4.3 LPGPIO port output data register (LPGPIO_ODR) . . . . . . . . . . . . . . . 590

14.4.4 LPGPIO port bit set/reset register (LPGPIO_BSRR) . . . . . . . . . . . . . . 590

14.4.5 LPGPIO port bit reset register (LPGPIO_BRR) . . . . . . . . . . . . . . . . . . 591

14.4.6 LPGPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

15 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 592

15.1 SYSCFG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

15.2 SYSCFG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592

15.2.1 I/O compensation cell management . . . . . . . . . . . . . . . . . . . . . . . . . . 592

15.2.2 SYSCFG TrustZone security and privilege . . . . . . . . . . . . . . . . . . . . . 593

15.3 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595

15.3.1 SYSCFG secure configuration register (SYSCFG_SECCFGR) . . . . . 595

15.3.2 SYSCFG configuration register 1 (SYSCFG_CFGR1) . . . . . . . . . . . . 596

15.3.3 SYSCFG FPU interrupt mask register (SYSCFG_FPUIMR) . . . . . . . . 597

15.3.4 SYSCFG CPU non-secure lock register (SYSCFG_CNSLCKR) . . . . . 598

15.3.5 SYSCFG CPU secure lock register (SYSCFG_CSLOCKR) . . . . . . . . 599

15.3.6 SYSCFG configuration register 2 (SYSCFG_CFGR2) . . . . . . . . . . . . 600

15.3.7 SYSCFG memory erase status register (SYSCFG_MESR) . . . . . . . . 601

15.3.8 SYSCFG compensation cell control/status register

(SYSCFG_CCCSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602

15.3.9 SYSCFG compensation cell value register (SYSCFG_CCVR) . . . . . . 603

15.3.10 SYSCFG compensation cell code register (SYSCFG_CCCR) . . . . . . 604

15.3.11 SYSCFG RSS command register (SYSCFG_RSSCMDR) . . . . . . . . . 605

15.3.12 SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

16 Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

Contents RM0456

18/3023 RM0456 Rev 2

16.2 Connection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608

16.3 Interconnection details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

16.3.1 Master to slave interconnection for timers . . . . . . . . . . . . . . . . . . . . . . 610

16.3.2 Triggers to ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610

16.3.3 ADC analog watchdogs as triggers to timers . . . . . . . . . . . . . . . . . . . . 612

16.3.4 Triggers to DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612

16.3.5 Triggers on MDF1 or ADF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

16.3.6 Timer break from MDF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

16.3.7 Clock sources to timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

16.3.8 Triggers to low-power timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

16.3.9 Blanking sources to comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

16.3.10 RTC wakeup as inputs to timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

16.3.11 USB OTG SOF as trigger to timers . . . . . . . . . . . . . . . . . . . . . . . . . . . 616

16.3.12 Comparators as inputs, trigger or break signals to timers . . . . . . . . . . 616

16.3.13 System errors as break signals to timers . . . . . . . . . . . . . . . . . . . . . . . 618

16.3.14 Timers generating IRTIM signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618

16.3.15 Triggers for communication peripherals . . . . . . . . . . . . . . . . . . . . . . . . 618

16.3.16 Triggers to GPDMA/LPDMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619

16.3.17 Internal analog signals to analog peripherals . . . . . . . . . . . . . . . . . . . 620

16.3.18 ADC data filtering by the MDF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

16.3.19 Clock source for the DAC sample and hold mode . . . . . . . . . . . . . . . . 621

16.3.20 Internal tamper sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621

16.3.21 Output from tamper to RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622

16.3.22 Encryption keys to AES/SAES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622

17 General purpose direct memory access controller (GPDMA) . . . . . . 623

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

17.2 GPDMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623

17.3 GPDMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

17.3.1 GPDMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624

17.3.2 GPDMA autonomous mode in low-power modes . . . . . . . . . . . . . . . . 625

17.3.3 GPDMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

17.3.4 GPDMA block requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

17.3.5 GPDMA triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

17.4 GPDMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

17.4.1 GPDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631

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RM0456 Contents

17.4.2 GPDMA channel state and direct programming without any linked-list 631

17.4.3 GPDMA channel suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . 632

17.4.4 GPDMA channel abort and restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

17.4.5 GPDMA linked-list data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

17.4.6 Linked-list item transfer execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

17.4.7 GPDMA channel state and linked-list programming

in run-to-completion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638

17.4.8 GPDMA channel state and linked-list programming in link step mode 641

17.4.9 GPDMA channel state and linked-list programming . . . . . . . . . . . . . . 648

17.4.10 GPDMA FIFO-based transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

17.4.11 GPDMA transfer request and arbitration . . . . . . . . . . . . . . . . . . . . . . . 657

17.4.12 GPDMA triggered transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661

17.4.13 GPDMA circular buffering with linked-list programming . . . . . . . . . . . . 662

17.4.14 GPDMA secure/non-secure channel . . . . . . . . . . . . . . . . . . . . . . . . . . 664

17.4.15 GPDMA privileged/unprivileged channel . . . . . . . . . . . . . . . . . . . . . . . 665

17.4.16 GPDMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665

17.4.17 GPDMA autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

17.5 GPDMA in debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

17.6 GPDMA in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

17.7 GPDMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

17.8 GPDMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670

17.8.1 GPDMA secure configuration register (GPDMA_SECCFGR) . . . . . . . 670

17.8.2 GPDMA privileged configuration register (GPDMA_PRIVCFGR) . . . . 671

17.8.3 GPDMA configuration lock register (GPDMA_RCFGLOCKR) . . . . . . . 672

17.8.4 GPDMA non-secure masked interrupt status register

(GPDMA_MISR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

17.8.5 GPDMA secure masked interrupt status register (GPDMA_SMISR) . . 673

17.8.6 GPDMA channel x linked-list base address register

(GPDMA_CxLBAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

17.8.7 GPDMA channel x flag clear register (GPDMA_CxFCR) . . . . . . . . . . 674

17.8.8 GPDMA channel x status register (GPDMA_CxSR) . . . . . . . . . . . . . . 675

17.8.9 GPDMA channel x control register (GPDMA_CxCR) . . . . . . . . . . . . . 677

17.8.10 GPDMA channel x transfer register 1 (GPDMA_CxTR1) . . . . . . . . . . 679

17.8.11 GPDMA channel x transfer register 2 (GPDMA_CxTR2) . . . . . . . . . . 683

17.8.12 GPDMA channel x block register 1 (GPDMA_CxBR1) . . . . . . . . . . . . 687

17.8.13 GPDMA channel x alternate block register 1 (GPDMA_CxBR1) . . . . . 688

17.8.14 GPDMA channel x source address register (GPDMA_CxSAR) . . . . . 691

Contents RM0456

20/3023 RM0456 Rev 2

17.8.15 GPDMA channel x destination address register (GPDMA_CxDAR) . . 693

17.8.16 GPDMA channel x transfer register 3 (GPDMA_CxTR3) . . . . . . . . . . 694

17.8.17 GPDMA channel x block register 2 (GPDMA_CxBR2) . . . . . . . . . . . . 695

17.8.18 GPDMA channel x linked-list address register (GPDMA_CxLLR) . . . . 696

17.8.19 GPDMA channel x alternate linked-list address register

(GPDMA_CxLLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698

17.8.20 GPDMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

18 Low-power direct memory access controller (LPDMA) . . . . . . . . . . . 702

18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

18.2 LPDMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

18.3 LPDMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

18.3.1 LPDMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

18.3.2 LPDMA autonomous mode in low-power modes . . . . . . . . . . . . . . . . . 703

18.3.3 LPDMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

18.3.4 LPDMA block requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704

18.3.5 LPDMA triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

18.4 LPDMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

18.4.1 LPDMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

18.4.2 LPDMA channel state and direct programming without

any linked-list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

18.4.3 LPDMA channel suspend and resume . . . . . . . . . . . . . . . . . . . . . . . . 708

18.4.4 LPDMA channel abort and restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709

18.4.5 LPDMA linked-list data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710

18.4.6 Linked-list item transfer execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711

18.4.7 LPDMA channel state and linked-list programming

in run-to-completion mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712

18.4.8 LPDMA channel state and linked-list programming in link step mode . 716

18.4.9 LPDMA channel state and linked-list programming . . . . . . . . . . . . . . . 722

18.4.10 LPDMA direct transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724

18.4.11 LPDMA transfer request and arbitration . . . . . . . . . . . . . . . . . . . . . . . 726

18.4.12 LPDMA triggered transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730

18.4.13 LPDMA circular buffering with linked-list programming . . . . . . . . . . . . 731

18.4.14 LPDMA secure/non-secure channel . . . . . . . . . . . . . . . . . . . . . . . . . . 733

18.4.15 LPDMA privileged/unprivileged channel . . . . . . . . . . . . . . . . . . . . . . . 734

18.4.16 LPDMA error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735

18.4.17 LPDMA autonomous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736

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