TI LMK04808：超低噪声时钟清理器与双环铂金 PLL 设计

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TI-LMK04808是一款高性能的低噪声时钟振荡器（PrecisionClock Conditioner）,专为满足下一代系统对超低相位随机误差（RMS Jitter）的要求而设计。这款设备的核心特点是其双环铂金™（Dual Loop PLLatinum™）架构，这种创新设计使得它能够在12kHz到20MHz频率范围内实现令人瞩目的111 femtoseconds (fs) RMS Jitter表现，这是业界领先的性能指标。 LMK04808集成了两个独立的PLL，每个PLL都具有出色的时钟生成、清理和分配能力，确保了在宽频率范围内的高精度。对于高频信号（如12kHz到20MHz），它能够提供111fs RMS Jitter，而对于低频信号（100Hz到20MHz），它仍能保持123fs RMS Jitter，这在许多应用中是至关重要的，例如数字信号处理、通信系统和数据转换器（如FPGA）中，稳定的时间基准对于信号同步至关重要。该器件支持多种输出时钟接口，包括CLKout4,5,6,7, CLKout2, CLKout0,1,以及专门用于FPGA的CLKin0输入，适应了不同模块的需求。它还可能包含晶体振荡器（Crystal or VCXO）作为备份参考时钟源，确保系统在主时钟发生故障时仍能维持稳定工作。此外，LMK04808还提供了其他功能，如PLL+VCO、Serializer/Deserializer（用于串行/并行数据转换）、CPLD（复杂可编程逻辑器件）以及针对特定应用的IF和IQ接口（用于模拟信号处理）。 LMK0480x系列包括LMK04803, LMK04805, LMK04806和LMK04808型号，这意味着用户可以根据项目需求选择最适合的版本。文档SNAS489K-MARCH2011–REVISEDDECEMBER2014提供了详细的技术文档，包括设计指南、工具与软件支持、以及样本下载和购买选项。同时，TI公司还提供了全面的技术支持和社区资源，帮助用户解决在使用过程中遇到的问题。 TI-LMK04808凭借其卓越的低噪声性能和广泛的时钟管理能力，是现代电子系统中精密时钟解决方案的理想选择。它的先进特性确保了系统在高速数据传输和信号处理中的精确同步，对于追求极致性能的设计师来说，这是一个不可或缺的组件。

GND

= | V

- V

= 2·V

Definition V

Definition for Output

Non-Inverting Clock

Inverting Clock

2·V

GND

= | V

- V

= 2·V

Definition V

Definition for Input

Non-Inverting Clock

Inverting Clock

2·V

LMK04803

LMK04805

LMK04806

LMK04808

SNAS489K –MARCH 2011–REVISED DECEMBER 2014

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7.2 Differential Voltage Measurement Terminology

The differential voltage of a differential signal can be described by two different definitions causing confusion

when reading datasheets or communicating with other engineers. This section will address the measurement and

description of a differential signal so that the reader will be able to understand and discern between the two

different definitions when used.

The first definition used to describe a differential signal is the absolute value of the voltage potential between the

inverting and non-inverting signal. The symbol for this first measurement is typically V

or V

depending on if

an input or output voltage is being described.

The second definition used to describe a differential signal is to measure the potential of the non-inverting signal

with respect to the inverting signal. The symbol for this second measurement is V

and is a calculated

parameter. Nowhere in the IC does this signal exist with respect to ground, it only exists in reference to its

differential pair. V

can be measured directly by oscilloscopes with floating references, otherwise this value can

be calculated as twice the value of V

as described in the first description.

Figure 4 illustrates the two different definitions side-by-side for inputs and Figure 5 illustrates the two different

definitions side-by-side for outputs. The V

and V

definitions show V

and V

DC levels that the non-inverting

and inverting signals toggle between with respect to ground. V

input and output definitions show that if the

inverting signal is considered the voltage potential reference, the non-inverting signal voltage potential is now

increasing and decreasing above and below the non-inverting reference. Thus the peak-to-peak voltage of the

differential signal can be measured.

and V

are often defined as volts (V) and V

is often defined as volts peak-to-peak (V

Figure 4. Two Different Definitions for Differential Input Signals

Figure 5. Two Different Definitions for Differential Output Signals

Refer to Application Note AN-912, Common Data Transmission Parameters and their Definitions (SNLA036) for

more information.

Product Folder Links: LMK04803 LMK04805 LMK04806 LMK04808

LMK04803

LMK04805

LMK04806

LMK04808

www.ti.com

SNAS489K –MARCH 2011–REVISED DECEMBER 2014

8 Detailed Description

8.1 Overview

In default mode of operation, dual PLL mode with internal VCO, the Phase Frequency Detector in PLL1

compares the active CLKinX reference divided by CLKinX_PreR_DIV and PLL1 R divider with the external

VCXO or crystal attached to the PLL2 OSCin port divided by PLL1 N divider. The external loop filter for PLL1

should be narrow to provide an ultra clean reference clock from the external VCXO or crystal to the

OSCin/OSCin* pins for PLL2.

The Phase Frequency Detector in PLL2 compares the external VCXO or crystal to the internal VCO after the

reference and feedback dividers. The VCXO or crystal on the OSCin input is divided by PLL2 R divider. The

feedback from the internal VCO is divided by the PLL2 Prescaler, the PLL2 N divider, and optionally the VCO

divider.

The bandwidth of the external loop filter for PLL2 should be designed to be wide enough to take advantage of

the low in-band phase noise of PLL2 and the low high offset phase noise of the internal VCO. The VCO output is

also placed on the distribution path for the Clock Distribution section. The clock distribution consists of 6 groups

of dividers and delays which drive 12 outputs. Each clock group allows the user to select a divide value, a digital

delay value, and an analog delay. The 6 groups drive programmable output buffers. Two groups allow their input

signal to be from the OSCin port directly.

When a 0-delay mode is used, a clock output will be passed through the feedback mux to the PLL1 N Divider for

synchronization and 0-delay.

When an external VCO mode is used, the Fin port will be used to input an external VCO signal. PLL2 Phase

comparison will now be with this signal divided by the PLL2 N divider and N2 pre-scaler. The VCO divider may

not be used. One less clock input is available when using an external VCO mode.

When a single PLL mode is used, PLL1 is powered down. OSCin is used as a reference to PLL2.

8.1.1 System Architecture

The dual loop PLL architecture of the LMK0480x provides the lowest jitter performance over the widest range of

output frequencies and phase noise integration bandwidths. The first stage PLL (PLL1) is driven by an external

reference clock and uses an external VCXO or tunable crystal to provide a frequency accurate, low phase noise

reference clock for the second stage frequency multiplication PLL (PLL2). PLL1 typically uses a narrow loop

bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the

same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated

along its path or from other circuits. This “cleaned” reference clock provides the reference input to PLL2.

The low phase noise reference provided to PLL2 allows PLL2 to operate with a wide loop bandwidth (50 kHz to

200 kHz). The loop bandwidth for PLL2 is chosen to take advantage of the superior high offset frequency phase

noise profile of the internal VCO and the good low offset frequency phase noise of the reference VCXO or

tunable crystal.

Ultra low jitter is achieved by allowing the external VCXO or crystal’s phase noise to dominate the final output

phase noise at low offset frequencies and the internal (or external) VCO’s phase noise to dominate the final

output phase noise at high offset frequencies. This results in best overall phase noise and jitter performance.

The LMK0480x allows subsets of the device to be used to increase the flexibility of device. These different

modes are selected using MODE: Device Mode. For instance:

• Dual Loop Mode - Typical use case of LMK04808. CLKinX used as reference input to PLL1, OSCin port is

connected to VCXO or tunable crystal.

• Single Loop Mode - Powers down PLL1. OSCin port is used as reference input.

• Clock Distribution Mode - Allows input of CLKin1 to be distributed to output with division, digital delay, and

analog delay.

See Device Functional Modes for more information on these modes.

Product Folder Links: LMK04803 LMK04805 LMK04806 LMK04808

LMK04803

LMK04805

LMK04806

LMK04808

SNAS489K –MARCH 2011–REVISED DECEMBER 2014

www.ti.com

Overview (continued)

8.1.2 PLL1 Redundant Reference Inputs (CLKin0/CLKin0* and CLKin1/CLKin1*)

The LMK0480x has two reference clock inputs for PLL1: CLKin0 and CLKin1. Ref Mux selects CLKin0 or

CLKin1. Automatic or manual switching occurs between the inputs.

CLKin0 and CLKin1 each have input dividers. The input divider allows different clock input frequencies to be

normalized so that the frequency input to the PLL1 R divider remains constant during automatic switching. By

programming these dividers such that the frequency presented to the input of the PLL1_R divider is the same

prevents the user from needing to reprogram the PLL1 R divider when the input reference is changed to another

CLKin port with a different frequency.

CLKin1 is shared for use as an external 0-delay feedback (FBCLKin), or for use with an external VCO (Fin).

Fast manual switching between reference clocks is possible with external pins Status_CLKin0 and

Status_CLKin1.

8.1.3 PLL1 Tunable Crystal Support

The LMK0480x integrates a crystal oscillator on PLL1 for use with an external crystal and varactor diode to

perform jitter cleaning.

The LMK0480x must be programmed to enable Crystal mode.

8.1.4 VCXO/CRYSTAL Buffered Outputs

The LMK0480x provides 2 dedicated outputs which are a buffered copy of the PLL2 reference input. This

reference input is typically a low noise VCXO or Crystal. When using a VCXO, this output can be used to clock

external devices such as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK0480x is programmed.

The OSCout0 buffer output type is programmable to LVDS, LVPECL, or LVCMOS. The OSCout1 buffer is fixed

to LVPECL.

The dedicated output buffers OSCout0 and OSCout1 can output frequency lower than the VCXO or Crystal

frequency by programming the OSC Divider. The OSC Divider value range is 2 to 8. Each OSCoutX can

individually choose to use the OSC Divider output or to bypass the OSC Divider.

Two clock output groups can also be programmed to be driven by OSCin. This allows a total of 4 additional

differential outputs to be buffered outputs of OSCin. When programmed in this way, a total of 6 differential

outputs can be driven by a buffered copy of OSCin.

VCXO/Crystal buffered outputs cannot be synchronized to the VCO clock distribution outputs. The assertion of

SYNC will still cause these outputs to become low temporarily. Since these outputs will turn off and on

asynchronously with respect to the VCO sourced clock outputs during a SYNC, it is possible for glitches to occur

on the buffered clock outputs when SYNC is asserted and unasserted. If the NO_SYNC_CLKoutX_Y bits are set

these outputs will not be affected by the SYNC event except that the phase relationship will change with the

other synchronized clocks unless a buffered clock output is used as a qualification clock during SYNC.

8.1.5 Frequency Holdover

The LMK0480x supports holdover operation to keep the clock outputs on frequency with minimum drift when the

reference is lost until a valid reference clock signal is re-established.

8.1.6 Integrated Loop Filter Poles

The LMK0480x features programmable 3rd and 4th order loop filter poles for PLL2. These internal resistors and

capacitor values may be selected from a fixed range of values to achieve either a 3rd or 4th order loop filter

response. The integrated programmable resistors and capacitors compliment external components mounted near

the chip.

These integrated components can be effectively disabled by programming the integrated resistors and capacitors

to their minimum values.

Product Folder Links: LMK04803 LMK04805 LMK04806 LMK04808

LMK04803

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SNAS489K –MARCH 2011–REVISED DECEMBER 2014

Overview (continued)

8.1.7 Internal VCO

The output of the internal VCO is routed to a mux which allows the user to select either the direct VCO output or

a divided version of the VCO for the Clock Distribution Path. This same selection is also fed back to the PLL2

phase detector through a prescaler and N-divider.

The mux selectable VCO divider has a divide range of 2 to 8 with 50% output duty cycle for both even and odd

divide values.

The primary use of the VCO divider is to achieve divides greater than the clock output divider supports alone.

8.1.8 External VCO Mode

The Fin/Fin* input allows an external VCO to be used with PLL2 of the LMK0480x.

Using an external VCO reduces the number of available clock inputs by one.

8.1.9 Clock Distribution

The LMK0480x features a total of 12 outputs driven from the internal or external VCO.

All VCO driven outputs have programmable output types. They can be programmed to LVPECL, LVDS, or

LVCMOS. When all distribution outputs are configured for LVCMOS or single ended LVPECL a total of 24

outputs are available.

If the buffered OSCin outputs OSCout0 and OSCout1 are included in the total number of clock outputs the

LMK0480x is able to distribute, then up to 14 differential clocks or up to 28 single ended clocks may be

generated with the LMK0480x.

The following sections discuss specific features of the clock distribution channels that allow the user to control

various aspects of the output clocks.

8.1.9.1 CLKout DIVIDER

Each clock group, which is a pair of outputs such as CLKout0 and CLKout1, has a single clock output divider.

The divider supports a divide range of 1 to 1045 (even and odd) with 50% output duty cycle. When divides of 26

or greater are used, the divider/delay block uses extended mode.

The VCO Divider may be used to reduce the divide needed by the clock group divider so that it may operate in

normal mode instead of extended mode. This can result in a small current saving if enabling the VCO Divider

allows 3 or more clock output divides to change from extended to normal mode.

8.1.9.2 CLKout Delay

See Clock Distribution section for details on both a fine (analog) and coarse (digital) delay for phase adjustment

of the clock outputs.

The fine (analog) delay allows a nominal 25 ps step size and range from 0 to 475 ps of total delay. Enabling the

analog delay adds a nominal 500 ps of delay in addition to the programmed value. When adjusting analog delay,

glitches may occur on the clock outputs being adjusted. Analog delay may not operate at frequencies above the

minimum-ensured maximum output frequency of 1536 MHz.

The coarse (digital) delay allows a group of outputs to be delayed by 4.5 to 12 clock distribution path cycles in

normal mode, or from 12.5 to 522 VCO cycles in extended mode. The delay step can be as small as half the

period of the clock distribution path by using the CLKoutX_Y_HS bit provided the output divide value is greater

than 1. For example, a 2-GHz VCO frequency without the use of the VCO divider results in 250 ps coarse tuning

steps.. The coarse (digital) delay value takes effect on the clock outputs after a SYNC event.

There are 3 different ways to use the digital (coarse) delay:

1. Fixed Digital Delay

2. Absolute Dynamic Digital Delay

3. Relative Dynamic Digital Delay

These are further discussed in Clock Distribution.

Product Folder Links: LMK04803 LMK04805 LMK04806 LMK04808

LMK04803

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SNAS489K –MARCH 2011–REVISED DECEMBER 2014

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Overview (continued)

8.1.9.3 Programmable Output Type

For increased flexibility all LMK0480x clock outputs (CLKoutX) and OSCout0 can be programmed to an LVDS,

LVPECL, or LVCMOS output type. OSCout1 is fixed as LVPECL.

Any LVPECL output type can be programmed to 700, 1200, 1600, or 2000 mVpp amplitude levels. The 2000

mVpp LVPECL output type is a Texas Instruments proprietary configuration that produces a 2000 mVpp

differential swing for compatibility with many data converters and is also known as 2VPECL.

8.1.9.4 Clock Output Synchronization

Using the SYNC input causes all active clock outputs to share a rising edge. See Clock Output Synchronization

(SYNC) for more information.

The SYNC event also causes the digital delay values to take effect.

8.1.10 0-Delay

The 0-delay mode synchronizes the input clock phase to the output clock phase. The 0-delay feedback may be

performed with an internal feedback loop from any of the clock groups or with an external feedback loop into the

FBCLKin port as selected by the FEEDBACK_MUX.

Without using 0-delay mode there will be D possible fixed phase relationships from clock input to clock output

depending on the clock output divide value.

Using an external 0-delay feedback reduces the number of available clock inputs by one.

8.1.11 Default Startup Clocks

Before the LMK0480x is programmed, CLKout8 is enabled and operating at a nominal frequency and CLKout6

and OSCout0 are enabled and operating at the OSCin frequency. These clocks can be used to clock external

devices such as microcontrollers, FPGAs, CPLDs, and so forth, before the LMK0480x is programmed.

For CLKout6 and OSCout0 to work before the LMK0480x is programmed, the device must not be using Crystal

mode.

8.1.12 Status Pins

The LMK0480x provides status pins which can be monitored for feedback or in some cases used for input

depending upon device programming. For example:

• The Status_Holdover pin may indicate if the device is in hold-over mode.

• The Status_CLKin0 pin may indicate the LOS (loss-of-signal) for CLKin0.

• The Status_CLKin0 pin may be an input for selecting the active clock input.

• The Status_LD pin may indicate if the device is locked.

The status pins can be programmed to a variety of other outputs including analog lock detect, PLL divider

outputs, combined PLL lock detect signals, PLL1 Vtune railing, readback, and so forth. Refer to the Programming

of this datasheet for more information. Default pin programming is captured in Table 18.

8.1.13 Register Readback

Programmed registers may be read back using the MICROWIRE interface. For readback, one of the status pins

must be programmed for readback mode.

At no time may registers be programed to values other than the valid states defined in the datasheet.

Product Folder Links: LMK04803 LMK04805 LMK04806 LMK04808

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