探索MSP430F2418微控制器的低功耗特性和功能

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本文档详细介绍了TI公司的MSP430F241x系列混合信号微控制器(Mixed-Signal Microcontroller)，包括一系列具有出色性能和低功耗特性的型号。MSP430F241x家族的特点包括： 1. **电源范围广泛**：该系列支持低电压操作，工作电压范围从1.8V到3.6V，非常适合电池供电的应用。 2. **便捷编程**：集成串行编程功能，无需额外外部编程电压，可以方便地进行程序加载和升级。 3. **超低功耗设计**： - **活跃模式**（Active Mode）下，如MSP430F2418在1MHz时，电流消耗仅为365μA，而在2.2V供电下，功耗非常低。 - **待机模式**（Standby Mode，如VLO）可降至0.5μA，MSP430F2417提供RAM保留下的关断模式，功耗更低至0.1μA。 - **唤醒时间**：从待机模式唤醒至执行操作所需时间小于1μs，这对于节省电能非常重要。 4. **高性能处理器架构**：基于16位RISC架构，指令周期时间为62.5 ns，提供了高效的计算能力。 5. **丰富的内部组件**： - **存储器**：大多数型号提供92KB至120KB的闪存和8KB至16KB的RAM，满足不同应用的需求。 - **数字与模拟转换**：MSP430F2418配备12位A/D转换器，具有内置参考、采样保持和自动扫描功能，以及双12位D/A转换器，支持同步操作。 - **定时器**：如MSP430F2419，具有两个16位定时器，A通道有三个捕获/比较寄存器，B通道有七个捕获/比较功能，并且B通道还包含阴影寄存器。 6. **高级特性**：如MSP430F2616，拥有16位Timer_A和Timer_B，Timer_B支持七个捕获/比较功能和阴影寄存器，增强定时和计数功能。 MSP430F241x系列微控制器是针对低功耗、高效能和多样化的I/O需求设计的，它们结合了精简的指令集、高效能硬件和丰富的内部资源，使得开发人员能够轻松构建各种嵌入式系统应用。文档SLAS541H-June2007-REVIEWED_MAY2011提供了完整的规格和使用指南，是开发人员理解和利用这些微控制器的理想参考文档。

MSP430F261x

MSP430F241x

SLAS541H –JUNE 2007– REVISED MAY 2011

www.ti.com

Special Function Registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

Legend rw: Bit can be read and written.

rw-0,1: Bit can be read and written. It is reset or set by PUC.

rw-(0,1): Bit can be read and written. It is reset or set by POR.

SFR bit is not present in device.

Table 6. Interrupt Enable Register 1 and 2

Address 7 6 5 4 3 2 1 0

00h ACCVIE NMIIE OFIE WDTIE

rw-0 rw-0 rw-0 rw-0

WDTIE Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in

interval timer mode.

OFIE Oscillator fault interrupt enable

NMIIE (Non)maskable interrupt enable

ACCVIE Flash access violation interrupt enable

Address 7 6 5 4 3 2 1 0

01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

rw-0 rw-0 rw-0 rw-0

UCA0RXIE USCI_A0 receive interrupt enable

UCA0TXIE USCI_A0 transmit interrupt enable

UCB0RXIE USCI_B0 receive interrupt enable

UCB0TXIE USCI_B0 transmit interrupt enable

Table 7. Interrupt Flag Register 1 and 2

Address 7 6 5 4 3 2 1 0

02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw-0 rw-(0) rw-(1) rw-1 rw-(0)

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on V

power-on or a reset condition at the RST/NMI pin in reset mode.

OFIFG Flag set on oscillator fault.

PORIFG Power-On Reset interrupt flag. Set on V

power-up.

RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on V

power-up.

NMIIFG Set via RST/NMI pin

Address 7 6 5 4 3 2 1 0

03h UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG

rw-1 rw-0 rw-1 rw-0

UCA0RXIFG USCI_A0 receive interrupt flag

UCA0TXIFG USCI_A0 transmit interrupt flag

UCB0RXIFG USCI_B0 receive interrupt flag

UCB0TXIFG USCI_B0 transmit interrupt flag

MSP430F261x

MSP430F241x

www.ti.com

SLAS541H –JUNE 2007– REVISED MAY 2011

Memory Organization

Table 8. Memory Organization

MSP430F2416 MSP430F2417 MSP430F2418 MSP430F2419

MSP430F2616 MSP430F2617 MSP430F2618 MSP430F2619

Memory Size 92KB 92KB 116KB 120KB

Main: interrupt vector Flash 0x0FFFF-0x0FFC0 0x0FFFF-0x0FFC0 0x0FFFF-0x0FFC0 0x0FFFF-0x0FFC0

Main: code memory Flash 0x18FFF-0x02100 0x19FFF-0x03100 0x1FFFF-0x03100 0x1FFFF-0x02100

RAM (total) Size 4KB 8KB 8KB 4KB

0x020FF-0x01100 0x030FF-0x01100 0x030FF-0x01100 0x020FF-0x01100

Extended Size 2KB 6KB 6KB 2KB

0x020FF-0x01900 0x030FF-0x01900 0x030FF-0x01900 0x020FF-0x01900

Mirrored Size 2KB 2KB 2KB 2KB

0x018FF-0x01100 0x018FF-0x01100 0x018FF-0x01100 0x018FF-0x01100

Information memory Size 256 Byte 256 Byte 256 Byte 256 Byte

Flash 0x010FF-0x01000 0x010FF-0x01000 0x010FF-0x01000 0x010FF-0x01000

Boot memory Size 1KB 1KB 1KB 1KB

ROM 0x00FFF-0x00C00 0x00FFF-0x00C00 0x00FFF-0x00C00 0x00FFF-0x00C00

RAM (mirrored at Size 2KB 2KB 2KB 2KB

0x18FF to 0x01100) 0x009FF-0x00200 0x009FF-0x00200 0x009FF-0x00200 0x009FF-0x00200

Peripherals 16-bit 0x001FF-0x00100 0x001FF-0x00100 0x001FF-0x00100 0x001FF-0x00100

8-bit 0x000FF-0x00010 0x000FF-0x00010 0x000FF-0x00010 0x000FF-0x00010

8-bit SFR 0x0000F-0x00000 0x0000F-0x00000 0x0000F-0x00000 0x0000F-0x00000

Bootstrap Loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to

the MSP430 memory via the BSL is protected by a user-defined password. For complete description of the

features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader (BSL)

User's Guide (SLAU319).

Table 9. BSL Pin Functions

PM, PN PACKAGE ZQW PACKAGE

BSL FUNCTION

PINS PINS

Data Transmit 13 - P1.1 H1 - P1.1

Data Receive 22 - P2.2 M3 - P2.2

Flash Memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The

CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also

called information memory.

• Segment A contains calibration data. After reset segment A is protected against programming and erasing. It

can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is

required.

• Flash content integrity check with marginal read modes

MSP430F261x

MSP430F241x

SLAS541H –JUNE 2007– REVISED MAY 2011

www.ti.com

Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

DMA Controller

The DMA controller allows movement of data from one memory address to another without CPU intervention. For

example, the DMA controller can be used to move data from the ADC12 conversion memory to RAM. Using the

DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power

consumption by allowing the CPU to remain in sleep mode without having to awaken to move data to or from a

peripheral.

Oscillator and System Clock

The clock system in the MSP430F241x and MSP430F261x family of devices is supported by the basic clock

module that includes support for a 32768-Hz watch crystal oscillator, an internal very low-power low-frequency

oscillator, an internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock

module is designed to meet the requirements of both low system cost and low power consumption. The internal

DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the

following clock signals:

• Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.

• Main clock (MCLK), the system clock used by the CPU.

• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.

Calibration Data Stored in Information Memory Segment A

Calibration data is stored for the DCO and for the ADC12. It is organized in a tag-length-value (TLV) structure.

Table 10. Tags Used by the TLV Structure

NAME ADDRESS VALUE DESCRIPTION

TAG_DCO_30 0x10F6 0x01 DCO frequency calibration at V

= 3 V and T

= 25°C at calibration

TAG_ADC12_1 0x10DA 0x08 ADC12_1 calibration tag

TAG_EMPTY - 0xFE Identifier for empty memory areas

Table 11. Labels Used by the ADC Calibration Structure

ADDRESS

LABEL CONDITION AT CALIBRATION / DESCRIPTION SIZE

OFFSET

CAL_ADC_25T85 INCHx = 0x1010, REF2_5 = 1, T

= 85°C word 0x000E

CAL_ADC_25T30 INCHx = 0x1010, REF2_5 = 1, T

= 30°C word 0x000C

CAL_ADC_25VREF_FACTOR REF2_5 = 1, T

= 30°C word 0x000A

CAL_ADC_15T85 INCHx = 0x1010, REF2_5 = 0, T

= 85°C word 0x0008

CAL_ADC_15T30 INCHx = 0x1010, REF2_5 = 0, T

= 30°C word 0x0006

CAL_ADC_15VREF_FACTOR REF2_5 = 0, T

= 30°C word 0x0004

CAL_ADC_OFFSET External V

REF

= 1.5 V, f

ADC12CLK

= 5 MHz word 0x0002

CAL_ADC_GAIN_FACTOR External V

REF

= 1.5 V, f

ADC12CLK

= 5 MHz word 0x0000

CAL_BC1_1MHZ - byte 0x0007

CAL_DCO_1MHZ - byte 0x0006

CAL_BC1_8MHZ - byte 0x0005

CAL_DCO_8MHZ - byte 0x0004

CAL_BC1_12MHZ - byte 0x0003

CAL_DCO_12MHZ - byte 0x0002

CAL_BC1_16MHZ - byte 0x0001

CAL_DCO_16MHZ - byte 0x0000

MSP430F261x

MSP430F241x

www.ti.com

SLAS541H –JUNE 2007– REVISED MAY 2011

Brownout, Supply Voltage Supervisor (SVS)

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and

power off. The SVS circuitry detects if the supply voltage drops below a user selectable level and supports both

supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM) (the device is

not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V

may not have

ramped to V

CC(min)

at that time. The user must ensure that the default DCO settings are not changed until V

reaches V

CC(min)

. If desired, the SVS circuit can be used to determine when V

reaches V

CC(min)

Digital I/O

There are up to eight 8-bit I/O ports implemented—ports P1 through P8:

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt condition is possible.

• Edge-selectable interrupt input capability for all the eight bits of port P1 and port P2.

• Read/write access to port-control registers is supported by all instructions.

• Each I/O has an individually programmable pullup/pulldown resistor.

• Ports P7/P8 can be accessed word-wise.

Watchdog Timer (WDT+)

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be disabled or configured as an interval timer and can

generate interrupts at selected time intervals.

Hardware Multiplier

The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8,

8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well as

signed and unsigned multiply and accumulate operations. The result of an operation can be accessed

immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are

required.

Universal Serial Communication Interface (USCI)

The USCI modules are used for serial data communication. The USCI module supports synchronous

communication protocols such as SPI (3 pin or 4 pin) or I

C, and asynchronous combination protocols such as

UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.

The USCI_A module provides support for SPI (3 pin or 4 pin), UART, enhanced UART, and IrDA.

The USCI_B module provides support for SPI (3 pin or 4 pin) and I

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