AD7124-8: 低功耗24位Σ-Δ型ADC，高精度模拟前端

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"AD7124-8是一款由Analog Devices公司生产的高精度、低功耗、低噪声24位Σ-Δ型模数转换器（ADC）。这款芯片适用于各种高精度测量应用，提供了8个差分输入或15个单端/伪差分输入的灵活性。AD7124-8的突出特点在于其内置的低噪声放大器，允许直接处理微弱信号，并且具备三种集成的功率模式，用户可以根据具体应用需求定制功耗、输出数据速率和均方根噪声。此外，器件还提供了多种滤波器选项，以适应不同的系统要求。" 详细说明: 1. **低噪声24位Σ-Δ型ADC**: AD7124-8采用Σ-Δ调制技术，提供24位分辨率，确保在高精度测量中捕捉到微小的信号变化。低噪声设计保证了信号的清晰度，使其适合于对噪声敏感的应用。 2. **灵活的输入配置**: AD7124-8支持8个差分输入通道或15个单端和伪差分输入通道，这使得它能适应多种输入信号类型和多通道测量系统。 3. **三种功率模式**: 用户可以选择低功耗、中等功耗和全功耗模式。在低功耗模式下，器件可以在1.17SPS（每秒采样率）时提供24nVrms的均方根噪声，而全功耗模式下，在9.4SPS时噪声为23nVrms，同时，输出数据速率也会随着功率模式的改变而变化。 4. **输出数据速率**: 根据功率模式的不同，AD7124-8的输出数据速率范围从1.17SPS到19,200SPS，满足不同实时性要求的系统需求。 5. **内置精密增益放大器和参考电压**: 内置的精密增益放大器（PGA）允许用户调整输入信号的增益，以优化信号处理。参考电压的集成有助于确保测量结果的精确性。 6. **滤波器选项**: AD7124-8提供了多种滤波器选项，这增加了设计的灵活性，用户可以根据系统的带宽和抗干扰需求选择合适的滤波设置。 7. **版权和技术支持**: 提供的文档反馈信息和Analog Devices的技术支持网址表明，用户可以获取最新的技术资料和帮助，以解决可能遇到的问题。总结来说，AD7124-8是一款高度集成的高精度ADC，其低功耗特性、灵活的输入配置、可定制的功率模式和滤波器选项，以及内置的增益放大器和参考电压，使其成为各种高精度测量应用的理想选择。无论是对噪声敏感的科学测量，还是对功耗有严格限制的工业自动化系统，AD7124-8都能提供出色的表现。

AD7124-8 Data Sheet

Rev. D | Page 14 of 92

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

NOTES

1. CONNECT EXPOSED PAD TO AV

REGCAPD

AIN5/IOUT/VBIAS/P4

IOV

DGND

AIN0/IOUT/VBIAS

AIN1/IOUT/VBIAS

AIN2/IOUT/VBIAS/P1

AIN3/IOUT/VBIAS/P2

AIN4/IOUT/VBIAS/P3

REGCAPA

REFOUT

AIN15/IOUT/VBIAS/REFIN2(–)

AIN14/IOUT/VBIAS/REFIN2(+)

AIN13/IOUT/VBIAS

AIN12/IOUT/VBIAS

AIN11/IOUT/VBIAS

CLK

SCLK

DIN

DOUT/RDY

SYNC

PSW

AIN6/IOUT/VBIAS

AIN7/IOUT/VBIAS

REFIN1(+)

REFIN1(–)

AIN8/IOUT/VBIAS

AIN9/IOUT/VBIAS

AIN10/IOUT/VBIAS

AD7124-8

TOP VIEW

(Not to Scale)

13048-009

Figure 9. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 REGCAPD Digital LDO Regulator Output. Decouple this pin to DGND with a 0.1 µF capacitor.

IOV

Serial Interface Supply Voltage, 1.65 V to 3.6 V. IOV

is independent of AV

. Therefore, the serial interface

can operate at 1.65 V with AV

at 3.6 V, for example.

3 DGND Digital Ground Reference Point.

4 AIN0/IOUT/VBIAS

Analog Input 0/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via

the configuration registers to be the positive or negative terminal of a differential or pseudo differential

input. Alternatively, the internal programmable excitation current source can be made available at this pin.

Either IOUT1 or IOUT0 can be switched to this output. A bias voltage midway between the analog power

supply rails can be generated at this pin.

5 AIN1/IOUT/VBIAS

Analog Input 1/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via

the configuration registers to be the positive or negative terminal of a differential or pseudo differential

input. Alternatively, the internal programmable excitation current source can be made available at this pin.

Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power

supply rails can be generated at this pin.

6 AIN2/IOUT/VBIAS/P1

Analog Input 2/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 1. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AV

and AV

7 AIN3/IOUT/VBIAS/P2

Analog Input 3/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 2. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AV

and AV

8 AIN4/IOUT/VBIAS/P3

Analog Input 4/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 3. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AV

and AV

Data Sheet AD7124-8

Rev. D | Page 15 of 92

Pin No. Mnemonic Description

9 AIN5/IOUT/VBIAS/P4

Analog Input 5/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 4. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AV

and AV

10 AIN6/IOUT/VBIAS

Analog Input 6/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via

the configuration registers to be the positive or negative terminal of a differential or pseudo differential

input. Alternatively, the internal programmable excitation current source can be made available at this pin.

Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power

supply rails can be generated at this pin.

11 AIN7/IOUT/VBIAS

Analog Input 7/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via

the configuration registers to be the positive or negative terminal of a differential or pseudo differential

input. Alternatively, the internal programmable excitation current source can be made available at this pin.

Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power

supply rails can be generated at this pin.

12 REFIN1(+)

Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−).

REFIN1(+) can be anywhere between AV

and AV

+ 1 V. The nominal reference voltage (REFIN1(+) −

REFIN1(−)) is 2.5 V, but the device functions with a reference from 1 V to AV

13 REFIN1(−) Negative Reference Input. This reference input can be anywhere between AV

and AV

− 1 V.

14 AIN8/IOUT/VBIAS

Analog Input 8/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

15 AIN9/IOUT/VBIAS

Analog Input 9/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

16 AIN10/IOUT/VBIAS

Analog Input 10/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

17 AIN11/IOUT/VBIAS

Analog Input 11/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

18 AIN12/IOUT/VBIAS

Analog Input 12/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

19 AIN13/IOUT/VBIAS

Analog Input 13/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

AIN14/IOUT/VBIAS/

REFIN2(+)

Analog Input 14/Output of Internal Excitation Current Source/Bias Voltage/Positive Reference Input. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin also functions as a

positive reference input for REFIN2(±). REFIN2(+) can be anywhere between AV

and AV

+ 1 V. The

nominal reference voltage (REFIN2(+) to REFIN2(−)) is 2.5 V, but the device functions with a reference from 1 V

to AV

AD7124-8 Data Sheet

Rev. D | Page 16 of 92

Pin No. Mnemonic Description

AIN15/IOUT/VBIAS/

REFIN2(−)

Analog Input 15/Output of Internal Excitation Current Source/Bias Voltage/Negative Reference Input. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin also functions as the

negative reference input for REFIN2(±). This reference input can be anywhere between AV

and AV

− 1 V.

22 REFOUT Internal Reference Output. The buffered output of the internal 2.5 V voltage reference is available on this pin.

23 AV

Analog Supply Voltage. The voltage on AV

is referenced to AV

. The differential between AV

and AV

must be between 2.7 V and 3.6 V in mid or low power mode and between 2.9 V and 3.6 V in full power

mode. AV

can be taken below 0 V to provide a dual power supply to the AD7124-8. For example, AV

can be tied to −1.8 V and AV

can be tied to +1.8 V, providing a ±1.8 V supply to the ADC.

24 REGCAPA Analog LDO Regulator Output. Decouple this pin to AV

with a 0.1 µF capacitor.

25 PSW Low-Side Power Switch to AV

26 AV

Analog Supply Voltage, Relative to AV

SYNC Synchronization Input. This pin is a logic input that allows synchronization of the digital filters and analog

modulators when using a number of AD7124-8 devices. When

SYNC is low, the nodes of the digital filter,

the filter control logic, and the calibration control logic are reset, and the analog modulator is held in a

reset state.

SYNC does not affect the digital interface but does reset RDY to a high state if it is low.

DOUT/

RDY Serial Data Output/Data Ready Output. DOUT/RDY functions as a serial data output pin to access the

output shift register of the ADC. The output shift register can contain data from any of the on-chip data or

control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a

conversion. If the data is not read after the conversion, the pin goes high before the next update occurs.

The DOUT/

RDY falling edge can also be used as an interrupt to a processor, indicating that valid data is

available. With an external serial clock, the data can be read using the DOUT/RDY pin. When CS is low, the

data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on

the SCLK rising edge.

29 DIN

Serial Data Input to the Input Shift Register on the ADC. Data in the input shift register is transferred to

the control registers within the ADC, with the register selection bits of the communications register

identifying the appropriate register.

30 SCLK

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK pin has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous

with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock

with the information being transmitted to or from the ADC in smaller batches of data.

31 CLK

Clock Input/Clock Output. The internal clock can be made available at this pin. Alternatively, the internal

clock can be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be

driven from a common clock, allowing simultaneous conversions to be performed.

CS Chip Select Input. This is an active low logic input that selects the ADC. Use CS to select the ADC in systems

with more than one device on the serial bus or as a frame synchronization signal in communicating with the

device.

CS can be hardwired low if the serial peripheral interface (SPI) diagnostics are unused, allowing the

ADC to operate in 3-wire mode with SCLK, DIN, and DOUT interfacing with the device.

EP Exposed Pad. Connect the exposed pad to AV

Data Sheet AD7124-8

Rev. D | Page 17 of 92

TERMINOLOGY

AINP

AINP refers to the positive analog input.

AINM

AINM refers to the negative analog input.

Integral Nonlinearity (INL)

INL is the maximum deviation of any code from a straight line

passing through the endpoints of the transfer function. The

endpoints of the transfer function are zero scale (not to be

confused with bipolar zero), a point 0.5 LSB below the first code

transition (000 … 000 to 000 … 001), and full scale, a point

0.5 LSB above the last code transition (111 … 110 to 111 …

111). The error is expressed in ppm of the full-scale range.

Gain Error

Gain error is the deviation of the last code transition (111 …

110 to 111 … 111) from the ideal AINP voltage (AINM +

REF

/gain − 3/2 LSBs). Gain error applies to both unipolar

and bipolar analog input ranges.

Gain error is a measure of the span error of the ADC. It

includes full-scale errors but not zero-scale errors. For unipolar

input ranges, it is defined as full-scale error minus unipolar

offset error; whereas for bipolar input ranges it is defined as

full-scale error minus bipolar zero error.

Offset Error

Offset error is the deviation of the first code transition from the

ideal AINP voltage (AINM + 0.5 LSB) when operating in the

unipolar mode.

In bipolar mode, offset error is the deviation of the midscale

transition (0111 … 111 to 1000 … 000) from the ideal AINP

voltage (AINM − 0.5 LSB).

Offset Calibration Range

In the system calibration modes, the AD7124-8 calibrates offset

with respect to the analog input. The offset calibration range

specification defines the range of voltages that the AD7124-8

can accept and still calibrate offset accurately.

Full-Scale Calibration Range

The full-scale calibration range is the range of voltages that the

AD7124-8 can accept in the system calibration mode and still

calibrate full scale correctly.

Input Span

In system calibration schemes, two voltages applied in sequence

to the AD7124-8 analog input define the analog input range.

The input span specification defines the minimum and

maximum input voltages from zero to full scale that the

AD7124-8 can accept and still calibrate gain accurately.

AD7124-8 Data Sheet

Rev. D | Page 18 of 92

TYPICAL PERFORMANCE CHARACTERISTICS

2500

500

1000

1500

2000

7FFFCE

7FFFCF

7FFFD0

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7FFFDA

7FFFDB

7FFFDC

OCCURRENCE

CODES (HEX)

10,000 SAMPLES

13048-010

Figure 10. Noise Histogram Plot (Full Power Mode, Post Filter, Output Data

Rate = 25 SPS, Gain = 1)

1200

1000

800

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7FFFC6

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OCCURRENCE

CODES (HEX)

10,000 SAMPLES

13048-012

Figure 11. Noise Histogram Plot (Mid Power Mode, Post Filter, Output Data

Rate = 25 SPS, Gain = 1)

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7FFFC1

7FFFC3

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7FFFCD

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7FFFDB

7FFFDD

7FFFDF

7FFFE1

7FFFE3

7FFFE5

7FFFE7

7FFFE9

7FFFEB

7FFFED

7FFFF0

7FFFF2

OCCURRENCE

CODES (HEX)

10,000 SAMPLES

13048-014

Figure 12. Noise Histogram Plot (Low Power Mode, Post Filter, Output Data

Rate = 25 SPS, Gain = 1)

350

300

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7FFFE9

7FFFFA

800002

800009

800011

800019

800020

800028

800030

800038

80003F

800047

80004F

800057

80005E

800066

80006E

800075

80007D

800085

80008D

800094

80009C

8000A4

OCCURRENCE

CODES (HEX)

10,000 SAMPLES

13048-011

Figure 13. Noise Histogram Plot (Full Power Mode, Post Filter, Output Data

Rate = 25 SPS, Gain = 128)

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8388394.0

8388452.8

8388469.6

8388486.4

8388503.2

8388520.0

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8388570.4

8388587.2

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8388755.2

8388772.0

8388788.8

8388805.6

OCCURRENCE

CODES (HEX)

10,000 SAMPLES

13048-013

Figure 14. Noise Histogram Plot (Mid Power Mode, Post Filter, Output Data

Rate = 25 SPS, Gain = 128)

400

100

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800012

800028

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800055

80006C

800083

800099

8000B0

8000C6

8000F3

80010A

800121

8000DD

OCCURRENCE

CODES (HEX)

10,000 SAMPLES

13048-015

Figure 15. Noise Histogram Plot (Low Power Mode, Post Filter, Output Data

Rate = 25 SPS, Gain = 128)

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