Intel®64和IA-32体系结构软件开发者手册：系统编程指南第3部分

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"Intel开发手册卷3详细介绍了Intel 64和IA-32架构的系统编程指南第三部分" Intel的64位和IA-32架构软件开发者手册是一套全面的技术文档，由九个卷组成，涵盖了从基本架构到指令集参考、系统编程等多个方面。这套手册是为软件开发者、系统架构师以及硬件工程师提供深入理解Intel处理器平台的关键参考资料。卷3C，即“系统编程指南，第三部分”，主要关注的是与系统级编程相关的主题。它包括但不限于以下关键知识点： 1. **内存管理**：这部分可能会涵盖虚拟地址空间的组织，页面表的管理，内存保护机制，以及如何有效地利用物理和虚拟内存。 2. **中断和异常处理**：手册会详细介绍如何处理硬件和软件中断，异常处理流程，以及中断描述符表（IDT）和中断服务例程（ISR）的配置。 3. **多处理器（SMP）系统**：在多核或多处理器环境中，如何协调和同步各个处理器的操作，包括总线锁定，中断处理，以及多处理器间的通信。 4. **电源管理和性能监控**：这部分可能涉及CPU功耗管理技术，如C状态（C1, C2, C3等），以及性能监控单元（PMU）的使用，以优化能效和性能。 5. **系统扩展和新技术**：可能涵盖Intel的扩展如VT-x（虚拟化技术），TXT（可信执行技术），以及SIMD（单指令多数据）指令集如SSE、AVX等。 6. **I/O编程**：I/O端口的访问，DMA（直接存储器访问）操作，以及现代PCIe等高速接口的使用方法。 7. **系统初始化和固件交互**：BIOS和UEFI的交互，初始化序列，以及固件接口的调用。 8. **安全性和稳定性**：可能包括数据加密技术，如AES-NI，以及系统的安全特性，如SMAP（Supervisor Mode Access Prevention）和SMX（Software Guard Extensions）。每个卷都提供了深入的技术细节，帮助开发者理解和利用Intel处理器的高级功能。同时，手册强调了正确评估设计需求的重要性，建议读者在实际应用中参考全部九卷内容。请注意，Intel的技术特性和优势取决于系统配置，可能需要启用的硬件、软件或服务激活。此外，计算机系统的安全性并非绝对，Intel不对数据丢失或系统损害造成的损失承担任何责任。用户在使用这些技术时，应遵守相关法律法规，并确保遵循最佳实践，以保护系统安全。

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VIRTUAL MACHINE CONTROL STRUCTURES

All other bits in this field are reserved, some to 0 and some to 1. Software should consult the VMX capability MSRs

IA32_VMX_PROCBASED_CTLS and IA32_VMX_TRUE_PROCBASED_CTLS (see Appendix A.3.2) to determine how

to set reserved bits. Failure to set reserved bits properly causes subsequent VM entries to fail (see Section

26.2.1.1).

The first processors to support the virtual-machine extensions supported only the 1-settings of bits 1, 4–6, 8, 13–

16, and 26. The VMX capability MSR IA32_VMX_PROCBASED_CTLS will always report that these bits must be 1.

Logical processors that support the 0-settings of any of these bits will support the VMX capability MSR

IA32_VMX_TRUE_PROCBASED_CTLS MSR, and software should consult this MSR to discover support for the 0-

settings of these bits. Software that is not aware of the functionality of any one of these bits should set that bit to 1.

Bit 31 of the primary processor-based VM-execution controls determines whether the secondary processor-based

VM-execution controls are used. If that bit is 0, VM entry and VMX non-root operation function as if all the

secondary processor-based VM-execution controls were 0. Processors that support only the 0-setting of bit 31 of

the primary processor-based VM-execution controls do not support the secondary processor-based VM-execution

controls.

15 CR3-load exiting In conjunction with the CR3-target controls (see Section 24.6.7), this control determines

whether executions of MOV to CR3 cause VM exits. See Section 25.1.3.

The first processors to support the virtual-machine extensions supported only the 1-setting

of this control.

16 CR3-store exiting This control determines whether executions of MOV from CR3 cause VM exits.

The first processors to support the virtual-machine extensions supported only the 1-setting

of this control.

19 CR8-load exiting This control determines whether executions of MOV to CR8 cause VM exits.

20 CR8-store exiting This control determines whether executions of MOV from CR8 cause VM exits.

21 Use TPR shadow Setting this control to 1 enables TPR virtualization and other APIC-virtualization features. See

Chapter 29.

22 NMI-window

exiting

If this control is 1, a VM exit occurs at the beginning of any instruction if there is no virtual-

NMI blocking (see Section 24.4.2).

23 MOV-DR exiting This control determines whether executions of MOV DR cause VM exits.

24 Unconditional I/O

exiting

This control determines whether executions of I/O instructions (IN, INS/INSB/INSW/INSD, OUT,

and OUTS/OUTSB/OUTSW/OUTSD) cause VM exits.

25 Use I/O bitmaps This control determines whether I/O bitmaps are used to restrict executions of I/O instructions

(see Section 24.6.4 and Section 25.1.3).

For this control, “0” means “do not use I/O bitmaps” and “1” means “use I/O bitmaps.” If the I/O

bitmaps are used, the setting of the “unconditional I/O exiting” control is ignored.

27 Monitor trap flag If this control is 1, the monitor trap flag debugging feature is enabled. See Section 25.5.2.

28 Use MSR bitmaps This control determines whether MSR bitmaps are used to control execution of the RDMSR

and WRMSR instructions (see Section 24.6.9 and Section 25.1.3).

For this control, “0” means “do not use MSR bitmaps” and “1” means “use MSR bitmaps.” If the

MSR bitmaps are not used, all executions of the RDMSR and WRMSR instructions cause

VM exits.

29 MONITOR exiting This control determines whether executions of MONITOR cause VM exits.

30 PAUSE exiting This control determines whether executions of PAUSE cause VM exits.

31 Activate secondary

controls

This control determines whether the secondary processor-based VM-execution controls are

used. If this control is 0, the logical processor operates as if all the secondary processor-based

VM-execution controls were also 0.

Table 24-6. Definitions of Primary Processor-Based VM-Execution Controls (Contd.)

Bit Position(s) Name Description

Vol. 3C 24-11

VIRTUAL MACHINE CONTROL STRUCTURES

Table 24-7 lists the secondary processor-based VM-execution controls. See Chapter 25 for more details of how

these controls affect processor behavior in VMX non-root operation.

Table 24-7. Definitions of Secondary Processor-Based VM-Execution Controls

Bit Position(s) Name Description

0 Virtualize APIC

accesses

If this control is 1, the logical processor treats specially accesses to the page with the APIC-

access address. See Section 29.4.

1 Enable EPT If this control is 1, extended page tables (EPT) are enabled. See Section 28.2.

2 Descriptor-table

exiting

This control determines whether executions of LGDT, LIDT, LLDT, LTR, SGDT, SIDT, SLDT, and

STR cause VM exits.

3 Enable RDTSCP If this control is 0, any execution of RDTSCP causes an invalid-opcode exception (#UD).

4 Virtualize x2APIC

mode

If this control is 1, the logical processor treats specially RDMSR and WRMSR to APIC MSRs (in

the range 800H–8FFH). See Section 29.5.

5 Enable VPID If this control is 1, cached translations of linear addresses are associated with a virtual-

processor identifier (VPID). See Section 28.1.

6 WBINVD exiting This control determines whether executions of WBINVD cause VM exits.

7 Unrestricted guest This control determines whether guest software may run in unpaged protected mode or in real-

address mode.

8APIC-register

virtualization

If this control is 1, the logical processor virtualizes certain APIC accesses. See Section 29.4 and

Section 29.5.

9Virtual-interrupt

delivery

This controls enables the evaluation and delivery of pending virtual interrupts as well as the

emulation of writes to the APIC registers that control interrupt prioritization.

10 PAUSE-loop exiting This control determines whether a series of executions of PAUSE can cause a VM exit (see

Section 24.6.13 and Section 25.1.3).

11 RDRAND exiting This control determines whether executions of RDRAND cause VM exits.

12 Enable INVPCID If this control is 0, any execution of INVPCID causes a #UD.

13 Enable

VM functions

Setting this control to 1 enables use of the VMFUNC instruction in VMX non-root operation. See

Section 25.5.5.

14 VMCS shadowing If this control is 1, executions of VMREAD and VMWRITE in VMX non-root operation may access

a shadow VMCS (instead of causing VM exits). See Section 24.10 and Section 30.3.

15 Enable ENCLS

exiting

If this control is 1, executions of ENCLS consult the ENCLS-exiting bitmap to determine whether

the instruction causes a VM exit. See Section 24.6.16 and Section 25.1.3.

16 RDSEED exiting This control determines whether executions of RDSEED cause VM exits.

17 Enable PML If this control is 1, an access to a guest-physical address that sets an EPT dirty bit first adds an

entry to the page-modification log. See Section 28.2.5.

18 EPT-violation #VE If this control is 1, EPT violations may cause virtualization exceptions (#VE) instead of VM exits.

See Section 25.5.6.

19 Conceal VMX non-

root operation from

Intel PT

If this control is 1, Intel Processor Trace suppresses data packets that indicate the use of

virtualization (see Chapter 36).

20 Enable

XSAVES/XRSTORS

If this control is 0, any execution of XSAVES or XRSTORS causes a #UD.

22 Mode-based

execute control for

EPT

If this control is 1, EPT execute permissions are based on whether the linear address being

accessed is supervisor mode or user mode. See Chapter 28.

25 Use TSC scaling This control determines whether executions of RDTSC, executions of RDTSCP, and executions

of RDMSR that read from the IA32_TIME_STAMP_COUNTER MSR return a value modified by the

TSC multiplier field (see Section 24.6.5 and Section 25.3).

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VIRTUAL MACHINE CONTROL STRUCTURES

All other bits in this field are reserved to 0. Software should consult the VMX capability MSR

IA32_VMX_PROCBASED_CTLS2 (see Appendix A.3.3) to determine which bits may be set to 1. Failure to clear

reserved bits causes subsequent VM entries to fail (see Section 26.2.1.1).

24.6.3 Exception Bitmap

The exception bitmap is a 32-bit field that contains one bit for each exception. When an exception occurs, its

vector is used to select a bit in this field. If the bit is 1, the exception causes a VM exit. If the bit is 0, the exception

is delivered normally through the IDT, using the descriptor corresponding to the exception’s vector.

Whether a page fault (exception with vector 14) causes a VM exit is determined by bit 14 in the exception bitmap

as well as the error code produced by the page fault and two 32-bit fields in the VMCS (the page-fault error-code

mask and page-fault error-code match). See Section 25.2 for details.

24.6.4 I/O-Bitmap Addresses

The VM-execution control fields include the 64-bit physical addresses of I/O bitmaps A and B (each of which are

4 KBytes in size). I/O bitmap A contains one bit for each I/O port in the range 0000H through 7FFFH; I/O bitmap B

contains bits for ports in the range 8000H through FFFFH.

A logical processor uses these bitmaps if and only if the “use I/O bitmaps” control is 1. If the bitmaps are used,

execution of an I/O instruction causes a VM exit if any bit in the I/O bitmaps corresponding to a port it accesses is

1. See Section 25.1.3 for details. If the bitmaps are used, their addresses must be 4-KByte aligned.

24.6.5 Time-Stamp Counter Offset and Multiplier

The VM-execution control fields include a 64-bit TSC-offset field. If the “RDTSC exiting” control is 0 and the “use

TSC offsetting” control is 1, this field controls executions of the RDTSC and RDTSCP instructions. It also controls

executions of the RDMSR instruction that read from the IA32_TIME_STAMP_COUNTER MSR. For all of these, the

value of the TSC offset is added to the value of the time-stamp counter, and the sum is returned to guest software

in EDX:EAX.

Processors that support the 1-setting of the “use TSC scaling” control also support a 64-bit TSC-multiplier field.

If this control is 1 (and the “RDTSC exiting” control is 0 and the “use TSC offsetting” control is 1), this field also

affects the executions of the RDTSC, RDTSCP, and RDMSR instructions identified above. Specifically, the contents

of the time-stamp counter is first multiplied by the TSC multiplier before adding the TSC offset.

See Chapter 27 for a detailed treatment of the behavior of RDTSC, RDTSCP, and RDMSR in VMX non-root operation.

24.6.6 Guest/Host Masks and Read Shadows for CR0 and CR4

VM-execution control fields include guest/host masks and read shadows for the CR0 and CR4 registers. These

fields control executions of instructions that access those registers (including CLTS, LMSW, MOV CR, and SMSW).

They are 64 bits on processors that support Intel 64 architecture and 32 bits on processors that do not.

In general, bits set to 1 in a guest/host mask correspond to bits “owned” by the host:

• Guest attempts to set them (using CLTS, LMSW, or MOV to CR) to values differing from the corresponding bits

in the corresponding read shadow cause VM exits.

• Guest reads (using MOV from CR or SMSW) return values for these bits from the corresponding read shadow.

Bits cleared to 0 correspond to bits “owned” by the guest; guest attempts to modify them succeed and guest reads

return values for these bits from the control register itself.

See Chapter 27 for details regarding how these fields affect VMX non-root operation.

Vol. 3C 24-13

VIRTUAL MACHINE CONTROL STRUCTURES

24.6.7 CR3-Target Controls

The VM-execution control fields include a set of 4 CR3-target values and a CR3-target count. The CR3-target

values each have 64 bits on processors that support Intel 64 architecture and 32 bits on processors that do not.

The CR3-target count has 32 bits on all processors.

An execution of MOV to CR3 in VMX non-root operation does not cause a VM exit if its source operand matches one

of these values. If the CR3-target count is n, only the first n CR3-target values are considered; if the CR3-target

count is 0, MOV to CR3 always causes a VM exit

There are no limitations on the values that can be written for the CR3-target values. VM entry fails (see Section

26.2) if the CR3-target count is greater than 4.

Future processors may support a different number of CR3-target values. Software should read the VMX capability

MSR IA32_VMX_MISC (see Appendix A.6) to determine the number of values supported.

24.6.8 Controls for APIC Virtualization

There are three mechanisms by which software accesses registers of the logical processor’s local APIC:

• If the local APIC is in xAPIC mode, it can perform memory-mapped accesses to addresses in the 4-KByte page

referenced by the physical address in the IA32_APIC_BASE MSR (see Section 10.4.4, “Local APIC Status and

Location” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A and Intel® 64

Architecture Processor Topology Enumeration).

• If the local APIC is in x2APIC mode, it can accesses the local APIC’s registers using the RDMSR and WRMSR

instructions (see Intel® 64 Architecture Processor Topology Enumeration).

• In 64-bit mode, it can access the local APIC’s task-priority register (TPR) using the MOV CR8 instruction.

There are five processor-based VM-execution controls (see Section 24.6.2) that control such accesses. There are

“use TPR shadow”, “virtualize APIC accesses”, “virtualize x2APIC mode”, “virtual-interrupt delivery”, and “APIC-

• APIC-access address (64 bits). This field contains the physical address of the 4-KByte APIC-access page.

If the “virtualize APIC accesses” VM-execution control is 1, access to this page may cause VM exits or be

virtualized by the processor. See Section 29.4.

The APIC-access address exists only on processors that support the 1-setting of the “virtualize APIC accesses”

VM-execution control.

• Virtual-APIC address (64 bits). This field contains the physical address of the 4-KByte virtual-APIC page.

The processor uses the virtual-APIC page to virtualize certain accesses to APIC registers and to manage virtual

interrupts; see Chapter 29.

Depending on the setting of the controls indicated earlier, the virtual-APIC page may be accessed by the

following operations:

— The MOV CR8 instructions (see Section 29.3).

— Accesses to the APIC-access page if, in addition, the “virtualize APIC accesses” VM-execution control is 1

(see Section 29.4).

— The RDMSR and WRMSR instructions if, in addition, the value of ECX is in the range 800H–8FFH (indicating

an APIC MSR) and the “virtualize x2APIC mode” VM-execution control is 1 (see Section 29.5).

If the “use TPR shadow” VM-execution control is 1, VM entry ensures that the virtual-APIC address is 4-KByte

aligned. The virtual-APIC address exists only on processors that support the 1-setting of the “use TPR shadow”

VM-execution control.

• TPR threshold (32 bits). Bits 3:0 of this field determine the threshold below which bits 7:4 of VTPR (see

Section 29.1.1) cannot fall. If the “virtual-interrupt delivery” VM-execution control is 0, a VM exit occurs after

an operation (e.g., an execution of MOV to CR8) that reduces the value of those bits below the TPR threshold.

See Section 29.1.2.

1. If the local APIC does not support x2APIC mode, it is always in xAPIC mode.

24-14 Vol. 3C

VIRTUAL MACHINE CONTROL STRUCTURES

The TPR threshold exists only on processors that support the 1-setting of the “use TPR shadow” VM-execution

control.

• EOI-exit bitmap (4 fields; 64 bits each). These fields are supported only on processors that support the 1-

setting of the “virtual-interrupt delivery” VM-execution control. They are used to determine which virtualized

writes to the APIC’s EOI register cause VM exits:

— EOI_EXIT0 contains bits for vectors from 0 (bit 0) to 63 (bit 63).

— EOI_EXIT1 contains bits for vectors from 64 (bit 0) to 127 (bit 63).

— EOI_EXIT2 contains bits for vectors from 128 (bit 0) to 191 (bit 63).

— EOI_EXIT3 contains bits for vectors from 192 (bit 0) to 255 (bit 63).

See Section 29.1.4 for more information on the use of this field.

• Posted-interrupt notification vector (16 bits). This field is supported only on processors that support the 1-

setting of the “process posted interrupts” VM-execution control. Its low 8 bits contain the interrupt vector that

is used to notify a logical processor that virtual interrupts have been posted. See Section 29.6 for more

information on the use of this field.

• Posted-interrupt descriptor address (64 bits). This field is supported only on processors that support the

1-setting of the “process posted interrupts” VM-execution control. It is the physical address of a 64-byte

aligned posted interrupt descriptor. See Section 29.6 for more information on the use of this field.

24.6.9 MSR-Bitmap Address

On processors that support the 1-setting of the “use MSR bitmaps” VM-execution control, the VM-execution control

fields include the 64-bit physical address of four contiguous MSR bitmaps, which are each 1-KByte in size. This

field does not exist on processors that do not support the 1-setting of that control. The four bitmaps are:

• Read bitmap for low MSRs (located at the MSR-bitmap address). This contains one bit for each MSR address

in the range 00000000H to 00001FFFH. The bit determines whether an execution of RDMSR applied to that

MSR causes a VM exit.

• Read bitmap for high MSRs (located at the MSR-bitmap address plus 1024). This contains one bit for each

MSR address in the range C0000000H toC0001FFFH. The bit determines whether an execution of RDMSR

applied to that MSR causes a VM exit.

• Write bitmap for low MSRs (located at the MSR-bitmap address plus 2048). This contains one bit for each

MSR address in the range 00000000H to 00001FFFH. The bit determines whether an execution of WRMSR

applied to that MSR causes a VM exit.

• Write bitmap for high MSRs (located at the MSR-bitmap address plus 3072). This contains one bit for each

MSR address in the range C0000000H toC0001FFFH. The bit determines whether an execution of WRMSR

applied to that MSR causes a VM exit.

A logical processor uses these bitmaps if and only if the “use MSR bitmaps” control is 1. If the bitmaps are used, an

execution of RDMSR or WRMSR causes a VM exit if the value of RCX is in neither of the ranges covered by the

bitmaps or if the appropriate bit in the MSR bitmaps (corresponding to the instruction and the RCX value) is 1. See

Section 25.1.3 for details. If the bitmaps are used, their address must be 4-KByte aligned.

24.6.10 Executive-VMCS Pointer

The executive-VMCS pointer is a 64-bit field used in the dual-monitor treatment of system-management interrupts

(SMIs) and system-management mode (SMM). SMM VM exits save this field as described in Section 34.15.2.

VM entries that return from SMM use this field as described in Section 34.15.4.

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