Chinese Journal of Electronics
Vol.28, No.5, Sept. 2019
Real-Time H.265/HEVC Intra Encoding with a
Configurable Architecture on FPGA Platform
∗
DING Dandan
1
, WANG Silong
2
, LIU Zoe
3
and YUAN Qingshu
1
(1. School of Information Science and Engineering, Hangzhou Normal University, Hangzhou 311121, China )
(2. College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China )
(3. Visionular Inc., Hangzhou 310012, China )
Abstract — This paper proposes a flexible design
scheme for H.265/HEVC encoding based on FPGA, which
allows an easy incorporation of a variety of algorithms
applied to different scenarios. In particular, we present
an H.265/HEVC intra encoder as an instantiation of
our proposed scheme. The key idea is to develop an
encoder system by configuring basic Processing elements
(PEs) of fundamental algorithms. Our intra encoder
using the flexible framework is structured with four-
stage CTU based pipeline. Pixel-level PEs are designed
to unify the intra prediction of 35 modes and a multi-
scale compatible transform array is proposed to process
variable size transform. 32 PEs are paralleled for intra
mode decision to support 35 combinations of modes
and partitions. In the reconstruction stage, 16 PEs are
paralleled for intra prediction and a 16 × 16 multiplier
array is configured for transforms of variable sizes with
a constant 16 pixels/cycle throughput. Implementation
results show that our proposed architecture costs about
63K Lookup tables and 62KB on-chip memories on Xilinx
Kintex-7 platform with the maximum working frequency
at 175MHz, which is sufficient for real-time encoding of
1920 × 1080 @60fps video at 160MHz. The flexibility and
extension capability of our framework provides a great
potential for future FPGA solutions serving for different
purposes.
Key words — H.265/HEVC, Configuration, Flexibility,
Intra prediction, FPGA.
I. Introduction
There has been an explosive growth in the usage
of Ultra high definition (UHD) videos, which leads
to a strong demand for more efficient video coding
standards. To meet such demands, the Joint collaborative
team on video coding (JCT-VC) has developed a new
video coding standard, so called as High efficiency video
coding (H.265/HEVC)
[1]
. Compared with H.264/AVC,
H.265/HEVC aims to reduce 40%–50% bitrate further
at the same visual quality
[2]
. To meet such a target,
H.265/HEVC employs more new coding tools, as well
as larger block sizes with more flexible partitions and
prediction modes to improve the coding efficiency.
Nonetheless, the high compression efficiency is achieved
at sacrifice of computational resources. Consequently,
H.265/HEVC encoders are several times more complex
than H.264/AVC
[3]
and hence pose a great challenge to
the implementation of real-time video encoding.
Recently, several works have addressed the trade-
off between computational complexity and high-efficiency
encoding through a joint-CPU-GPU framework
[4–10]
,
which mostly leverage the use of parallel optimization in
the level of Coding tree unit (CTU), Coding unit (CU),
or Predicting unit (PU). Differently, the ASIC/FPGA
design concerns the fine parallelism in pixel level. It is
thus challenging to develop an optimized ASIC/FPGA en-
coder. Several state-of-the-art ASIC-based H.265/HEVC
encoder solutions have been published, most of which are
focused on the intra encoder
[11,12]
. Different from ASICs,
FPGA design is further constrained by the total available
resource and frequency. Moreover, it is also challenging
to achieve high throughput on FPGA platforms.
Miyazawa et al.
[13]
develop an FPGA based proto-
type system that can achieve real-time encoding perfor-
mance for 1080p, 10-bit video at 60fps. Unfortunately,
the circuit consumption and working frequency is not
provided. The intra architecture by Atapattu et al.
[14]
works at 140MHz with 83k Lookup tables (LUTs) cost on
FPGA and can encode 1080p videos at 30fps. To enhance
∗
Manuscript Received Dec. 26, 2017; Accepted Sept. 18, 2018. This work is supported by the National Key Research and Development
Program of China (No.2017YFB1002803), and the National Natural Science Foundation of China (No.61602145).
© 2019 Chinese Institute of Electronics. DOI:10.1049/cje.2019.06.020