FPGA平台上实时H.265/HEVC内编码的可配置架构

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"基于FPGA的实时H.265/HEVC内编码可配置架构" 在数字视频编码领域，H.265/High Efficiency Video Coding（HEVC）标准是目前广泛采用的一种高效编码方式，它能以更低的带宽传输相同质量的视频，大大提升了压缩效率。本研究论文主要探讨了在FPGA（Field-Programmable Gate Array）平台上实现H.265/HEVC内编码的实时可配置架构。 FPGA是一种可编程逻辑器件，具有灵活、高效和实时处理的优点，特别适合于视频编码这样的计算密集型任务。该论文提出了一种灵活的设计方案，该方案允许根据不同的应用场景轻松地集成各种算法。核心思想是通过配置基本的处理元素（Processing Elements, PEs）来构建一个编码系统，这些PEs是基本算法的基础。在H.265/HEVC内编码器的设计中，采用了四阶段基于CTU（Coding Tree Unit）的流水线结构。CTU是编码的基本单元，可以处理不同大小的图像块。论文中的内预测模块设计了像素级PEs，能够统一处理35种不同的内预测模式，这大大提高了编码的灵活性和效率。同时，为了适应不同尺寸的变换，他们还提出了一种多尺度兼容的变换数组，能够处理变量大小的变换操作，这是对传统固定大小变换的改进。此外，32个PEs的使用表明，这种架构能够在保持高性能的同时，有效地利用FPGA的并行处理能力，实现视频编码的实时性。这种灵活的架构不仅优化了编码性能，而且降低了设计复杂性，使得系统可以根据需要进行动态调整，以适应不断变化的编码需求。这篇论文的研究成果为FPGA上的H.265/HEVC编码提供了一个高效且可扩展的解决方案，对于FPGA开发者和视频编码技术的研究者来说，具有很高的参考价值。通过这种方式，可以在不牺牲性能的前提下，降低硬件成本，并且为未来的视频编码标准升级提供了便利的平台。

Chinese Journal of Electronics

Vol.28, No.5, Sept. 2019

Real-Time H.265/HEVC Intra Encoding with a

Conﬁgurable Architecture on FPGA Platform

∗

DING Dandan

, WANG Silong

, LIU Zoe

and YUAN Qingshu

(1. School of Information Science and Engineering, Hangzhou Normal University, Hangzhou 311121, China )

(2. College of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China )

(3. Visionular Inc., Hangzhou 310012, China )

Abstract — This paper proposes a ﬂexible design

scheme for H.265/HEVC encoding based on FPGA, which

allows an easy incorporation of a variety of algorithms

applied to diﬀerent scenarios. In particular, we present

an H.265/HEVC intra encoder as an instantiation of

our proposed scheme. The key idea is to develop an

encoder system by conﬁguring basic Processing elements

(PEs) of fundamental algorithms. Our intra encoder

using the ﬂexible framework is structured with four-

stage CTU based pipeline. Pixel-level PEs are designed

to unify the intra prediction of 35 modes and a multi-

scale compatible transform array is proposed to process

variable size transform. 32 PEs are paralleled for intra

mode decision to support 35 combinations of modes

and partitions. In the reconstruction stage, 16 PEs are

paralleled for intra prediction and a 16 × 16 multiplier

array is conﬁgured for transforms of variable sizes with

a constant 16 pixels/cycle throughput. Implementation

results show that our proposed architecture costs about

63K Lookup tables and 62KB on-chip memories on Xilinx

Kintex-7 platform with the maximum working frequency

at 175MHz, which is suﬃcient for real-time encoding of

1920 × 1080 @60fps video at 160MHz. The ﬂexibility and

extension capability of our framework provides a great

potential for future FPGA solutions serving for diﬀerent

purposes.

Key words — H.265/HEVC, Conﬁguration, Flexibility,

Intra prediction, FPGA.

I. Introduction

There has been an explosive growth in the usage

of Ultra high deﬁnition (UHD) videos, which leads

to a strong demand for more eﬃcient video coding

standards. To meet such demands, the Joint collaborative

team on video coding (JCT-VC) has developed a new

video coding standard, so called as High eﬃciency video

coding (H.265/HEVC)

[1]

. Compared with H.264/AVC,

H.265/HEVC aims to reduce 40%–50% bitrate further

at the same visual quality

[2]

. To meet such a target,

H.265/HEVC employs more new coding tools, as well

as larger block sizes with more ﬂexible partitions and

prediction modes to improve the coding eﬃciency.

Nonetheless, the high compression eﬃciency is achieved

at sacriﬁce of computational resources. Consequently,

H.265/HEVC encoders are several times more complex

than H.264/AVC

[3]

and hence pose a great challenge to

the implementation of real-time video encoding.

Recently, several works have addressed the trade-

oﬀ between computational complexity and high-eﬃciency

encoding through a joint-CPU-GPU framework

[4–10]

which mostly leverage the use of parallel optimization in

the level of Coding tree unit (CTU), Coding unit (CU),

or Predicting unit (PU). Diﬀerently, the ASIC/FPGA

design concerns the ﬁne parallelism in pixel level. It is

thus challenging to develop an optimized ASIC/FPGA en-

coder. Several state-of-the-art ASIC-based H.265/HEVC

encoder solutions have been published, most of which are

focused on the intra encoder

[11,12]

. Diﬀerent from ASICs,

FPGA design is further constrained by the total available

resource and frequency. Moreover, it is also challenging

to achieve high throughput on FPGA platforms.

Miyazawa et al.

[13]

develop an FPGA based proto-

type system that can achieve real-time encoding perfor-

mance for 1080p, 10-bit video at 60fps. Unfortunately,

the circuit consumption and working frequency is not

provided. The intra architecture by Atapattu et al.

[14]

works at 140MHz with 83k Lookup tables (LUTs) cost on

FPGA and can encode 1080p videos at 30fps. To enhance

∗

Manuscript Received Dec. 26, 2017; Accepted Sept. 18, 2018. This work is supported by the National Key Research and Development

Program of China (No.2017YFB1002803), and the National Natural Science Foundation of China (No.61602145).

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