嵌入式系统设计新流程：RTOS与ESL的集成

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"本文探讨了如何通过增强实时操作系统（RTOS）集成来提升系统级设计流程的效率和质量，特别是在嵌入式系统设计领域。作者Rohan Kangralkar在论文中介绍了将Real-Time Executive for Multiprocessor Systems (RTEMS)这一常见RTOS整合到System-on-Chip Environment (SCE)工具中的工作，以支持ARM和Blackfin处理器的系统设计。" 嵌入式系统设计的复杂性随着技术的发展日益增加，电子系统级（ESL）设计方法和系统级设计语言（SLDL）应运而生，旨在以更高的抽象层次处理设计问题。在这样的背景下，软件部分的重要性凸显，RTOS和多线程应用程序成为嵌入式系统的核心组成部分。这些系统的性能和效率不仅取决于硬件，还依赖于软件的调度、任务分配和优先级设置等因素。 RTOS在嵌入式系统中的作用至关重要，因为它管理着任务的执行顺序，确保关键任务的及时完成。RTEMS是一个开源的RTOS，专为多处理器系统设计，适合在严格的实时环境中使用。通过将其集成到ESL工具SCE中，设计师可以更早地在设计流程中考虑RTOS的影响，从而优化硬件和软件的协同工作。论文的主要贡献是开发了一个流程，允许在虚拟平台上对RTEMS上的应用程序进行仿真和测试。虚拟平台基于合成的硬件模型，提供了一个近似的物理硬件环境，使得软件开发者能够在实际硬件可用之前进行测试、分析和调试。这种早期验证有助于减少设计错误，提高整体系统的可靠性，并降低开发成本。在ESL流程中，RTEMS的集成使得设计者能够模拟和分析RTOS的动态调度行为，以及任务和优先级分配对系统性能的影响。这有助于在设计空间探索阶段做出更明智的决策，优化系统资源的分配，减少延迟，并确保满足实时性的需求。此外，论文还强调了与教授和专家的合作，如Thesis Advisor Gunar Schirner，Thesis Reader David R. Kaeli和Kaushik Roy Chowdhury，他们的专业知识和指导对论文的研究和成果产生了积极影响。通过这个研究，Kangralkar为嵌入式系统设计提供了一个增强的工具集，有望促进未来更高效、更可靠的系统级设计实践。总结来说，这篇论文详细阐述了如何通过增强RTOS的集成来改进系统级设计流程，特别是在嵌入式系统中。通过整合RTEMS到ESL工具SCE，设计师可以更早地考虑软件层面的问题，从而在设计初期就优化硬件和软件的交互，降低复杂性和风险，提高整体系统性能。

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CHAPTER 1. INTRODUCTION

Figure 1.1: Hardware, Software and System Design Gap(Source:[59]).

nology and HW design and shown as HW Design Gap in Figure 1.1. Similarly at present software

design is reported to increase by about 2x every 24 months. But current need for software design

growth is estimated at 2x over 10 months. Thus there is software design productivity gap and hard-

ware design productivity gap. Combining both productivity gaps, as shown in Figure 1.1, results in

a large system design productivity gap. These conﬂicting demands lead to a signiﬁcant productiv-

ity gap. Therefore, new approaches are needed to dramatically increase design productivity and to

close the productivity gap. One such approach is utilizing hierarchy and designing at a higher level

of abstraction, which enables constructing larger and more complex systems.

1.2 System Level Design

Design complexity of embedded systems is exploding due to the market demand for more

complex features and tight coupling between hardware and software. Due to rapid advances in

technology there is high pressure of short time-to-market for many consumer electronics embedded

products. However the traditional way of designing hardware system components followed by

software development separately, does not optimally parallelize design task hence consumes time

causing industries to miss marketing deadlines. Also achieving the set functional and non-functional

goals, involves analyzing a multi-dimensional design space which is difﬁcult to achieve in traditional

methodology due to increased cost and time. System Level Design addresses these challenges by

using a holistic approach. Instead of designing the hardware and software components separately,

a complete embedded system is designed together enabling tight coupling between hardware and

software. An essential aspect of System Level Design (SLD) is the hardware and software co-

CHAPTER 1. INTRODUCTION

design, where both aspects of the system are concurrently designed aiding in faster time to market

and tight coupling between hardware and software.

Most modern day embedded systems consists of heterogeneous processors, interconnect-

ing bus and custom hardware components. Selection of components depends on functional and

non-functional objectives of the embedded system. A system may contain a mix of software run-

ning on one or more generic processors and specialized hardware to meet the set objectives. With

a system-level view, the embedded system design starts early with a speciﬁc algorithmic system

description independent of a particular hardware-software implementation. System Level Design

Languages (SLDL) is able to capture both hardware and software features at a higher abstraction

level. Jointly designing both aspects has the potential for exploiting the acceleration achieved by

hardware and ﬂexibility provided by software for more efﬁcient designs. For exploring the design

space quickly SLDL are used along with Electronic System Level (ESL) Design tools. The ESL

process facilitates automatic synthesis, rapid prototyping and facilitates larger design space explo-

ration.

1.3 Background

1.3.1 System on Chip Development Environment

System-on-Chip Environment (SCE) [25] is an ESL tool. This tool allows system design-

ers to capture system level speciﬁcation as a composition of behaviors. Behaviors are then trans-

formed into models by the specify-explore-reﬁne engine. The generated models are fully functional

and are validated for functionality and performance with varying accuracy and simulation speed.

Since reﬁnement is done automatically, the system designer can focus efforts on system design it-

self. Consequently, automated generation and validation allows designers to perform architectural

exploration in a larger design space.

SCE not only performs vertical synthesis of models with increasing accuracy but also

allows horizontal exploration of PE, mapping of tasks and connectivity. The Figure 1.2 gives a

brief overview of SCE design methodology. The embedded system designer captures the speciﬁ-

cation of the application algorithm via SLDL (SPECC [34]) models as composition of behaviors

communicating via abstract communication channels. The speciﬁcation model is purely functional

model, free of any architectural implementation details. The model focuses on capturing the algo-

rithmic behavior and allows a functional validation of the application. Since the speciﬁcation model

CHAPTER 1. INTRODUCTION

but all communication between the processing elements are still un-timed.

The next step in the reﬁnement is the scheduling reﬁnement. This reﬁnement allows the

designer to select suitable scheduling policy for the tasks executing on the processing elements. The

scheduling capabilities range from static scheduling, which allows most predictability without us-

ing an OS, to a priority based dynamic scheduling based on Real Time Operating System (RTOS).

Software task on a processing element can be scheduled statically or dynamically. If the embedded

system designer selects static scheduling then an RTOS is not selected instead the task are serialized

to execute as a state machine. Most modern embedded systems have task that are created dynami-

cally and interact with the environment dynamically. Static scheduling does not support the dynamic

characteristic of tasks. In SCE an abstract RTOS model is used to emulate the dynamic scheduling

behavior of tasks. The priority based scheduling allows the system designer to assign priority to

tasks executing on processors. A high level abstract RTOS model [19] provides the key features

that deﬁne a dynamic scheduling behavior independent of any speciﬁc RTOS implementation. The

RTOS model aids in exploring the priority and also may model RTOS timing for switching between

tasks.

The communication reﬁnement allows the system designer to explore bus interconnect

between the processing elements. Earlier deﬁned abstract communication channels are replaced by

busses models. Pin accurate model or Transaction accurate model of the bus is inserted between the

processing elements. The pin accurate model contains cycle accurate timing information about the

selected protocol whereas Transaction accurate models only the transactions. The model resulting

from the communication reﬁnement includes communication stack for the selected bus implemen-

tation. The pin accurate bus contains the arbitration and the access logic for a bus master or bus

slave. Thus the model now has high timing accuracy on the bus transaction.

To summarize, the Specify-Explore-Reﬁne starts at speciﬁcation model and passes

through computation, scheduling and communication reﬁnement stages. Each reﬁnement stage

captures the designers decision into models. The tools include information collected from previous

stages of reﬁnement into the models. These models called Transaction Level Model (TLM) con-

tain architectural and functional behavior information necessary for the synthesis engine to perform

software/hardware synthesis.

The synthesis step concludes the design ﬂow. The hardware synthesis generates the RTL

model of hardware component. The hardware synthesis uses a HW database of RTL components for

synthesizing a cycle accurate description of each custom hardware processing element. Similarly

the software synthesis uses a SW database. From the SW database, speciﬁc code for the selected

CHAPTER 1. INTRODUCTION

RTOS and drivers for communication are compiled along with the generated application code to

generate target binary code. The SW database also contains Instruction Set Simulator (ISS) for

the generic processing elements. The software synthesis generates ISS-based system model for

executing and validating the generated target binary code. The resulting combination gives a cycle

accurate execution of computation and communication of the embedded system. As a result of this

theses, additional RTOS is added to software database. The section 1.3.2 gives the brief overview

of the importance of an RTOS in modern embedded systems.

1.3.2 Real-Time Operating Systems

To manage the hardware resources operating systems are used as an additional abstraction

layer. Operating systems are special computer programs to manage computer resources. Modern

operating systems perform task management, memory management, task synchronization and com-

munication. They manage resources and provide an interface for the application to use computing

resources.

In process of managing the computing resources operating systems add an overhead to

the overall application execution. But the overhead amortizes over the productivity gain that can be

achieved by using the resource management features provided by the operating system. As a result

Operating Systems are being used for increased productivity. Embedded system have tight cost

constrains and computation power is expensive. But now-a-days with advances in semiconductor

technology the cost of computing resources is decreasing. Embedded systems are now designed

with slightly higher processing power budget to accommodate operating system overhead. This has

enabled operating systems to penetrate into domain of embedded systems where computation.

An embedded system is a specialized computer system designed to perform some spe-

ciﬁc task. These tasks often have real-time interaction with the environment in which the systems

execute. Embedded system usually has timing and resource constrains. Traditional OS lack pre-

dictability because they were designed for non-critical desktop systems. As a result specialized

operating systems with addition of timing constrain called Real Time Operating System (RTOS)

were developed. RTOS are playing important role in time critical embedded systems. Real-time

embedded systems are widely used in the domain of military, telecommunication, aviation, auto-

motive, medical and industrial automation. RTOS provides all standard OS features like task

management, memory management, task synchronization, communication. But in addition to stan-

dard OS features RTOS guarantee to execute the OS features deterministically. Designers can reuse

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嵌入式系统设计新流程：RTOS与ESL的集成

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