SNUG India 2009 4 Synthesis of Ultra-High-Performance Designs
1 Introduction
In this paper, we present our experiences in synthesizing high-performance blocks at AMD.
The paper is divided into four broad sections:
Synthesis-friendly one-hot RTL coding style
Advantages of non-uniform metal stack in a high-performance design
A few optimization tricks in physical synthesis
Usage of max capacitance limits
Synthesis tools are influenced by RTL coding style and it is important to adopt good coding styles.
One-hot muxes are pervasively used in most processors’ implementations to improve timing. The pa-
per presents problems for a given RTL coding style and present three different solutions with examples
to infer deterministically one-hot mux.
As we move to deeper sub-micron processes, interconnect delays dominate major portion of the clock
cycle. To achieve high performance, you might go for a metal stack that is not uniform, or increase the
metal layer or the cross-section area, which decreases delay. You can route a longer net with less de-
lay, so you can afford to place cells far from one another with minimal impact on net delay in a non-
uniform metal stack. However, the IC compiler optimizes based on average resistance and average
capacitance of all metal layers. This paper discusses a methodology to achieve best results when the
metal stack is not uniform.
Further, we discuss a few optimization tricks in physical synthesis like clock skewing/ gating and
min width. In the last section, the criticality of max capacitance in terms of QOR is discussed.