MKR3256M1688MBD：4GB DDR3L SDRAM芯片手册详解
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更新于2024-06-19
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MKR3256M1688MBD是一款高性能的4GB DDR3L SDRAM芯片，它由32Mx8 banks x 16位I/O组成，旨在提供高速数据传输和低功耗解决方案。该芯片适用于各种嵌入式系统和应用，特别适合那些对内存性能有较高要求的设备，如工业控制器、物联网设备等。
这款芯片的主要特性包括：
1. **电源规格**：支持1.35V至0.065V/0.1V或1.5V±0.075V的VDD电压，以及与之相匹配的VDDQ电压，确保了在不同工作条件下稳定运行。
2. **标准兼容性**：遵循DDR3/L SDRAM规范，保证了数据操作的准确性和一致性。
3. **内存配置**：拥有8个内部银行和1个内存排，提供了灵活的存储容量管理。
4. **速度等级**：最高可达DDR3/L-1600或DDR3/L-1866，支持PC3-12800和PC3-14900的高速数据传输速率。
5. **接口特性**：采用双向差分数据 strobe 和8位预取功能，提升数据读写效率；同时支持突发长度（BL）动态切换，可以选择BL8或BC4模式。
6. **终端技术**：内置On-Die Termination (ODT) 用于优化信号完整性。
7. **可编程时序参数**：允许用户设置CAS（读取）延迟（CL）、附加延迟（AL）和写入CAS延迟（CWL），以适应不同的系统需求。
8. **环保合规**：符合RoHS指令，降低了对环境的影响。
9. **温度范围**：工作温度在-55°C到+85°C之间，刷新周期在-55°C至+85°C下为64ms，+85°C至+105°C下为32ms，确保了宽温范围内的稳定工作。
总体来说，MKR3256M1688MBD芯片凭借其出色的性能、低功耗特性和高度可编程性，是设计工程师在选择内存解决方案时的理想选择，尤其是在对功耗敏感且需要高数据吞吐量的嵌入式应用中。在使用过程中，开发者需注意根据芯片规格进行正确的电气设计和编程设置，以充分利用其全部潜力。
6
MKR3256M1688MBB/SBB
Ball Description
Symbol
Type
Function
CK, /CK
Input
Clock: CK and /CK are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and negative
edge of /CK. Output (read) data is referenced to the crossings of CK and /CK
CKE
Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock
signals and device input buffers and output drivers. Taking CKE Low provides
Pre-charge Power-Down and Self Refresh operation (all banks idle), or Active
Power-Down (Row Active in any bank). CKE is asynchronous for self-refresh exit.
After V
REFCA
has become stable during the power on and initialization
sequence, it must be maintained during all operations (including Self-Refresh).
CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, /CK, ODT and CKE are disabled during Power Down. Input
buffers, excluding CKE, are disabled during Self Refresh.
/CS
Input
Chip Select: All commands are masked when /CS is registered HIGH. /CS
provides for external Rank selection on systems with multiple Ranks. /CS is
considered part of the command code.
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination resistance
internal to the DDR3/L SDRAM. When enabled, ODT is only applied to each
DQ, DQS, /DQS and DM. The ODT pin will be ignored if the Mode Register
(MR1) is programmed to disable ODT.
/RAS, /CAS, /WE
Input
Command Inputs: /RAS, /CAS and /WE (along with /CS) define the
command being entered.
UDM, LDM
Input
Input Data Mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH coincident with that input data during a
Write access. DM is sampled on both edges of DQS.
BA0~ BA2
Input
Bank Address Inputs: BA0-BA2 define the bank to which an Active, Read,
Write or Pre-charge command is being applied. Bank address also determines if
the mode register or extended mode register is to be accessed during a MRS
cycle.
A0~ A14
Input
Address Inputs: Provide the row address for Active commands and the column
address for Read/Write commands to select one location out of the memory
array in the respective bank. The address inputs also provide the op-code during
Mode Register Set commands. (A10/AP and A12/BC have additional functions,
see below)
A10 / AP
Input
Auto Pre-charge: A10 is sampled during Read/Write commands to determine
whether Auto pre-charge should be performed to the accessed bank after the
Read/Write operation (HIGH: Auto pre-charge; LOW: No Auto pre-charge). A10
is sampled during a Pre-charge command to determine whether the Pre-charge
applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to
be pre-charged, the bank is selected by bank addresses.
A12 / BC
Input
Burst Chop: A12 is sampled during Read and Write commands to determine if
burst chop (on-the-fly) will be performed. (HIGH: no burst chop, LOW: burst
chopped). See command truth table for details.
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