TMS320C6000 DSP I2C模块参考手册

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"DM642 I2C参考手册——TMS320C6000 DSP家族中的I2C模块技术指南" 本文档详细介绍了TMS320C6000 DSP家族中的Inter-Integrated Circuit (I2C) 模块。I2C总线是一种通信协议，由Philips（现NXP半导体）开发，主要用于微控制器和其他设备之间的短距离、低速率通信。该协议允许主设备与一个或多个从设备进行数据交换，常用于系统内部的传感器、时钟、存储器等组件的连接。 DM642是TMS320C6000系列中的一个高性能数字信号处理器，它集成了I2C模块，以便与其他支持I2C协议的器件进行通信。本参考手册的目标读者应已对I2C总线规范有一定的了解，文档将深入讲解如何在DM642上使用和配置I2C模块。文档的主要内容可能包括以下几个方面： 1. **I2C总线协议**：介绍I2C协议的基本原理，包括Start和Stop条件、数据传输方向、地址识别以及ACK/NAK机制。 2. **DM642的I2C模块架构**：描述DM642内部I2C模块的硬件结构，如时钟发生器、数据收发器、总线接口等组件的工作方式。 3. **操作模式**：涵盖不同类型的I2C操作模式，如标准模式（100kbps）、快速模式（400kbps）和高速模式（3.4Mbps），以及如何在DM642上设置这些模式。 4. **配置和控制**：详述如何通过寄存器配置I2C模块，包括时钟频率设定、中断控制、总线仲裁以及错误处理机制。 5. **通信实例**：提供实际应用中的通信示例，展示如何在DM642上编程实现与从设备的交互，如读写从设备内存、初始化和校验过程。 6. **故障排查和错误处理**：讨论可能出现的通信问题，如总线冲突、超时错误和数据不一致，并提供相应的解决策略。 7. **兼容性和兼容设备**：列出与DM642 I2C模块兼容的外部设备，以及如何确保与这些设备的兼容性。 8. **安全和稳定性**：强调TI对产品的质量保证，尽管TI对硬件性能按照销售时的规格进行了保证，但并不承担因应用协助或客户产品设计导致的责任。用户需确保其产品设计符合I2C协议和DM642的数据手册要求。本参考手册是DM642开发者和系统集成工程师的重要资源，它提供了全面的I2C模块使用指导，帮助实现高效、可靠的I2C通信，从而充分发挥DM642 DSP在各种嵌入式系统中的潜力。在设计和实施I2C通信方案时，务必参考此手册以确保正确理解和应用I2C模块的特性。

Functional Overview

Inter-Integrated Circuit (I2C) ModuleSPRU175D

2 Functional Overview

Each device connected to an I

C-bus, including any C6000 DSP connected

to the bus with an I2C module, is recognized by a unique address. Each device

can operate as either a transmitter or a receiver, depending on the function of

the device. In addition, a device connected to the I

C-bus can also be consid-

ered as the master or the slave when performing data transfers. Note that a

master device is the device that initiates a data transfer on the bus and gener-

ates the clock signals to permit that transfer. During this transfer, any device

addressed by this master is considered a slave. The I2C module supports the

multi-master mode, in which one or more devices capable of controlling an

C-bus can be connected to the same I

C-bus.

For data communication, the I2C module has a serial data pin (SDA) and a

serial clock pin (SCL), as shown in Figure 2. These two pins carry information

between the C6000 device and other devices connected to the I

C-bus. The

SDA and SCL pins both are bidirectional. They each must be connected to a

positive supply voltage using a pull-up resistor. When the bus is free, both pins

are high. The driver of these two pins has an open-drain configuration to

perform the required wired-AND function.

The I2C module consists of the following primary blocks:

- A serial interface: one data pin (SDA) and one clock pin (SCL)

- Data registers to temporarily hold receive data and transmit data traveling

between the SDA pin and the CPU or the EDMA controller

- Control and status registers

- A peripheral data bus interface to enable the CPU and the EDMA control-

ler to access the I2C module registers

- A clock synchronizer to synchronize the I2C input clock (from the DSP

clock generator) and the clock on the SCL pin, and to synchronize data

transfers with masters of different clock speeds

- A prescaler to divide down the input clock that is driven to the I2C module

- A noise filter on each of the two pins, SDA and SCL

- An arbitrator to handle arbitration between the I2C module (when it is a

master) and another master

- Interrupt generation logic, so that an interrupt can be sent to the CPU

- EDMA event generation logic, so that activity in the EDMA controller can

be synchronized to data reception and data transmission in the I2C module

Operational Details

Inter-Integrated Circuit (I2C) Module

SPRU175D

Table 1. Operating Modes of the I2C Module

Operating Mode Description

Slave-receiver mode The I2C module is a slave and receives data from a master. All slave modules

begin in this mode.

In this mode, serial data bits received on SDA are shifted in with the clock pulses

that are generated by the master. As a slave, the I2C module does not generate

the clock signal, but it can hold SCL low while the intervention of the DSP is

required (RSFULL = 1 in I2CSTR) after data has been received.

Slave-transmitter mode The I2C module is a slave and transmits data to a master.

This mode can only be entered from the slave-receiver mode; the I2C module

must first receive a command from the master. When you are using any of the

7-bit/10-bit addressing formats, the I2C module enters its slave-transmitter mode

if the slave address is the same as its own address (in I2COAR) and the master

has transmitted R/W

= 1. As a slave-transmitter, the I2C module then shifts the

serial data out on SDA with the clock pulses that are generated by the master.

While a slave, the I2C module does not generate the clock signal, but it can hold

SCL low while the intervention of the DSP is required (XSMT = 0 in I2CSTR) after

data has been transmitted.

Master-receiver mode The I2C module is a master and receives data from a slave.

This mode can only be entered from the master-transmitter mode; the I2C module

must first transmit a command to the slave. When you are using any of the

7-bit/10-bit addressing formats, the I2C module enters its master-receiver mode

after transmitting the slave address and R/W

= 1. Serial data bits on SDA are

shifted into the I2C module with the clock pulses generated by the I2C module on

SCL. The clock pulses are inhibited and SCL is held low when the intervention of

the DSP is required (RSFULL = 1 in I2CSTR) after data has been received.

Master-transmitter mode

The I2C module is a master and transmits control information and data to a slave.

All master modules begin in this mode.

In this mode, data assembled in any of the 7-bit/10-bit addressing formats is

shifted out on SDA. The bit shifting is synchronized with the clock pulses

generated by the I2C module on SCL. The clock pulses are inhibited and SCL is

held low when the intervention of the DSP is required (XSMT = 0 in I2CSTR) after

data has been transmitted.

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