CLRC663：多协议接触式读写器IC技术规格解析

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"CLR663数据手册是关于一款专用于POS设备的接触式读卡器集成电路解决方案的详细文档，该芯片全面符合ISO 14443、ISO 15693和FeliCa标准，适用于低功耗设计（如接入设备和手持设备）。它还支持额外的安全应用SAM，采用HVQFN32封装，优化尺寸，提供5.0V输出功率以确保最大的RF稳定性。此外，CLR663具备高达848kbits的高速通信能力，适用于快速交易，且已获得支付和电子政务应用的认证。该芯片的首批样品在2010年底推出。" 本文档主要介绍了CLR663接触式读卡器/写卡器集成电路的功能特性和电气规格。CLR663是一款针对13.56MHz频段的高集成度收发器IC，支持多种操作模式： 1. **读写模式**：支持ISO/IEC14443A（MIFARE）标准，包括MIFARE Classic 1K、4K、Ultralight、Ultralight C及MIFARE Plus等。 2. **读写模式**：支持ISO/IEC14443B标准。 3. **读写模式**：支持JISX6319-4（与FeliCa兼容）。 4. **被动启动模式**：根据ISO/IEC18092标准，允许卡片或标签主动发起通信。 5. **读写模式**：支持ISO/IEC15693标准，如ICODE EPC UID/EPC OTP。 6. **读写模式**：支持ISO/IEC18000-3模式3/EPC Class-1HF。 CLR663内部的发射器可以驱动一个读卡器/写卡器天线，无需额外的主动电路即可与符合ISO/IEC14443A/MIFARE标准的卡片和应答器通信。数字模块负责处理完整的ISO/IEC14443A帧格式和错误检测功能，包括奇偶校验和CRC校验。此外，该芯片设计考虑了低功耗，适合便携式和手持设备，封装紧凑，有利于设备小型化。输出功率为5.0V，可确保RF信号的稳定性，以实现最佳的读卡性能。高速波特率高达848kbits/s，极大地提升了交易速度，适用于高效的数据传输场景。同时，CLR663已通过认证，可用于支付系统和电子政府应用，保证了其在安全和合规性方面的可靠性。 CLR663是一款强大的、多功能的接触式读卡器IC，集成了多种标准的支持，适用于广泛的非接触式智能卡应用，包括但不限于支付系统、身份验证、门禁控制和公共交通支付等领域。其高效的性能和广泛的兼容性使其成为开发非接触式应用的理想选择。

Product data sheet

COMPANY PUBLIC

Rev. 3.5 — 5 September 2012

171135 16 of 137

NXP Semiconductors

CLRC663

Contactless reader IC

8.3.5 EPC-UID/UID-OTP functionality

The physical parameters are described in Table 11.

Data coding and framing according to EPC global 13.56 MHz ISM (industrial, scientific

and medical) Band Class 1 Radio Frequency Identification Tag Interface Specification

(Candidate Recommendation, Version 1.0.0).

8.3.6 ISO/IEC 18000-3 mode 3/ EPC Class-1 HF functionality

The ISO/IEC 18000-3 mode 3/ EPC Class-1 HF is not described in this document. For a

detailed explanation of the protocol, refer to the ISO/IEC 18000-3 mode 3/ EPC Class-1

HF standard.

8.3.7 ISO/IEC 18092 mode

The CLRC663 supports Passive Initiator Communication mode at the transfer speeds

106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the ISO/IEC 18092 standard.

• Passive communication mode means that the target answers to an initiator command

in a load modulation scheme. The initiator is active in terms of generating the RF field.

• Initiator: generates RF field at 13.56 MHz and starts the ISO/IEC 18092

communication.

• Target: responds to initiator command either in a load modulation scheme in Passive

communication mode or using a self generated and self modulated RF field for Active

Communication mode.

Table 11. Communication overview for EPC/UID

Communication

direction

Signal type Transfer speed

26.48 kbit/s 52.96 kbit/s

Reader to card (send

data from the

CLRC663 to a card)

reader side modulation 10 % to 30 % ASK

bit encoding RTZ

bit length 37.76 s

Card to reader

(CLRC663 receives

data from a card)

card side modulation single subcarrier load

modulation

bit length 18.88 s

bit encoding Manchester coding

Product data sheet

COMPANY PUBLIC

Rev. 3.5 — 5 September 2012

171135 19 of 137

NXP Semiconductors

CLRC663

Contactless reader IC

8.4.2 SPI interface

8.4.2.1 General

The CLRC663 acts as a slave during the SPI communication. The SPI clock SCK has to

be generated by the master. Data communication from the master to the slave uses the

Line MOSI. Line MISO is used to send data back from the CLRC663 to the master.

A serial peripheral interface (SPI compatible) is supported to enable high speed

communication to a host. The implemented SPI compatible interface is according to a

standard SPI interface. The SPI compatible interface can handle data speed of up to 10

Mbit/s. In the communication with a host CLRC663 acts as a slave receiving data from the

external host for register settings and to send and receive data relevant for the

communication on the RF interface.

On both data lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI line

shall be stable on rising edge of the clock line (SCK) and is allowed to change on falling

edge. The same is valid for the MISO line. Data is provided by the CLRC663 on the falling

edge and is stable on the rising edge.The polarity of the clock is low at SPI idle.

8.4.2.2 Read data

To read out data from the CLRC663 by using the SPI compatible interface the following

byte order has to be used.

The first byte that is sent defines the mode (LSB bit) and the address.

Table 14. Connection scheme for detecting the different interface types

Pin Pin Symbol UART SPI I

C I

C-L

28 IF0 RX MOSI ADR1 ADR1

29 IF1 - SCK SCL SCL

30 IF2 TX MISO ADR2 SDA

31 IF3 1 NSS SDA ADR2

26 IFSEL0 0 0 1 1

27 IFSEL1 0 1 0 1

Fig 12. Connection to host with SPI

001aal998

READER IC

IF1

SCK

IF0

MOSI

IF2

MISO

IF3

NSS

Table 15. Byte Order for MOSI and MISO

byte 0 byte 1 byte 2 byte 3 to n-1 byte n byte n+1

MOSI address 0 address 1 address 2 …….. address n 00h

MISO X data 0 data 1 …….. data n  1data n

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CLRC663：多协议接触式读写器IC技术规格解析

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