Atmega1280：高性能AVR微控制器详解

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Atmega1280是一款高性能、低功耗的Atmel AVR 8位微控制器，它基于先进的RISC架构设计，提供了卓越的处理能力。这款微控制器具备以下关键特性： 1. **强大的指令集与高效执行**：Atmega1280采用135条高效的单时钟周期指令，能够实现快速处理，支持高达16 MHz的16 MIPS吞吐量，满足实时应用的需求。 2. **存储器容量与非易失性存储**： - 它拥有64K、128K或256K字节的可系统编程闪存，用于长期存储程序代码。 - 内置4K字节的EEPROM（电可擦除只读存储器），具有出色的耐用性和数据保留能力，可在85°C下保持20年的数据完整性，在25°C下可达100年。 - 内部包含8K字节的SRAM（静态随机访问内存），方便运行时的数据处理。 - 为了增加安全性，提供了独立的锁定位选项的可选引导代码区域。 3. **内嵌编程功能**：通过芯片上的内嵌Bootloader实现固件在系统编程(ISP)，支持真正在写入过程中读取的操作，以及编程锁定机制来保护软件安全。 4. **扩展存储支持**：最多可支持64K字节的外部内存空间，增加了设备的存储灵活性。 5. **Atmel QTouch库集成**：该微控制器内置Atmel QTouch库，支持电容触摸按钮、滑块和轮盘的检测，以及多达64个感应通道，便于构建触控界面的交互设计。 6. **JTAG接口**：Atmega1280符合IEEE 1149.1标准，提供了边界扫描功能，便于调试和硬件级编程，包括对闪存、EEPROM、熔丝和锁定位的编程。 Atmega1280是一款集高效处理能力、大容量存储、高级编程功能和丰富的外设支持于一体的微控制器，广泛应用于工业控制、物联网(IoT)设备、消费电子和嵌入式系统开发等领域，特别适合对性能、可靠性和易用性有高要求的应用项目。

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

2549Q–AVR–02/2014

7.6.1 RAMPZ – Extended Z-pointer Register for ELPM/SPM

For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 7-4. Note

that LPM is not affected by the RAMPZ setting.

Figure 7-4. The Z-pointer used by ELPM and SPM

The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero.

For compatibility with future devices, be sure to write these bits to zero.

7.6.2 EIND – Extended Indirect Register

For EICALL/EIJMP instructions, the Indirect-pointer to the subroutine/routine is a concatenation of EIND, ZH, and

ZL, as shown in Figure 7-5. Note that ICALL and IJMP are not affected by the EIND setting.

Figure 7-5. The Indirect-pointer used by EICALL and EIJMP

The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero.

For compatibility with future devices, be sure to write these bits to zero.

7.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the

CPU clock clk

CPU

, directly generated from the selected clock source for the chip. No internal clock division is used.

Figure 7-6 on page 17 shows the parallel instruction fetches and instruction executions enabled by the Harvard

architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS

per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per

power-unit.

Bit 765432 1 0

0x3B (0x5B)

RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0

RAMPZ

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value000000 0 0

Bit

(Individually)

707070

RAMPZ ZH ZL

Bit (Z-pointer) 23 16 15 8 7 0

Bit 765432 1 0

0x3C (0x5C) EIND7 EIND6 EIND5 EIND4 EIND3 EIND2 EIND1 EIND0 EIND

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value000000 0 0

Bit

(Individually)

707070

EIND ZH ZL

Bit (Indirect-

pointer)

23 16 15 8 7 0

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

2549Q–AVR–02/2014

Figure 7-6. The Parallel Instruction Fetches and Instruction Executions

Figure 7-7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using

two register operands is executed, and the result is stored back to the destination register.

Figure 7-7. Single Cycle ALU Operation

7.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a

separate program vector in the program memory space. All interrupts are assigned individual enable bits which

must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the

interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits

BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 325 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors.

The complete list of vectors is shown in “Interrupts” on page 101. The list also determines the priority levels of the

different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next

is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash sec-

tion by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 101 for more

information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the

BOOTRST Fuse, see “Memory Programming” on page 325.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user soft-

ware can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current

interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For

these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt

handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writ-

ing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding

interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clk

CPU

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

2549Q–AVR–02/2014

flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit

is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is

set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not nec-

essarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will

not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction

before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when

returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be

executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example

shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pend-

ing interrupts, as shown in this example.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

2549Q–AVR–02/2014

8. AVR Memories

This section describes the different memories in the ATmega640/1280/1281/2560/2561. The AVR architecture has

two main memory spaces, the Data Memory and the Program Memory space. In addition, the

ATmega640/1280/1281/2560/2561 features an EEPROM Memory for data storage. All three memory spaces are

linear and regular.

8.1 In-System Reprogrammable Flash Program Memory

The ATmega640/1280/1281/2560/2561 contains 64K/128K/256K bytes On-chip In-System Reprogrammable Flash

memory for program storage, see Figure 8-1. Since all AVR instructions are 16 bit or 32 bit wide, the Flash is orga-

nized as 32K/64K/128K × 16. For software security, the Flash Program memory space is divided into two sections,

Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega640/1280/1281/2560/2561

Program Counter (PC) is 15/16/17 bits wide, thus addressing the 32K/64K/128K program memory locations. The

operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in

“Boot Loader Support – Read-While-Write Self-Programming” on page 310. “Memory Programming” on page 325

contains a detailed description on Flash data serial downloading using the SPI pins or the JTAG interface.

Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program

Memory instruction description and ELPM - Extended Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 16.

8.2 SRAM Data Memory

Figure 8-2 on page 22 shows how the ATmega640/1280/1281/2560/2561 SRAM Memory is organized.

The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be sup-

ported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space

from $060 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The first 4,608/8,704 Data Memory locations address both the Register File, the I/O Memory, Extended I/O Mem-

ory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard

I/O Memory, then 416 locations of Extended I/O memory and the next 8,192 locations address the internal data

SRAM.

An optional external data SRAM can be used with the ATmega640/1280/1281/2560/2561. This SRAM will occupy

an area in the remaining address locations in the 64K address space. This area starts at the address following the

internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the lowest 4,608/8,704 bytes, so

when using 64Kbytes (65,536 bytes) of External Memory, 60,478/56,832 Bytes of External Memory are available.

See “External Memory Interface” on page 27 for details on how to take advantage of the external memory map.

Figure 8-1. Program Flash Memory Map

Address (HEX)

Application Flash Section

Boot Flash Section

0x7FFF/0xFFFF/0x1FFFF

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