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μPD720201/μPD720202：Renesas USB 3.0主机控制器数据手册

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μPD720201/μPD720202是Renesas公司推出的第三代USB 3.0主机控制器，符合USB 3.0规范以及Intel的可扩展主机控制器接口(xHCI)标准。这两款芯片旨在降低功耗并提供更小的封装尺寸，特别适合集成到移动计算设备，如笔记本电脑和超薄型计算机，以增强它们的USB 3.0功能。 μPD720201支持多达四个USB 3.0 SuperSpeed端口，而μPD720202则支持两个这样的高速接口。这些控制器利用PCI Express Gen 2系统总线，这意味着系统设计师可以轻松地将它们集成到具有PCI Express接口的系统中，从而在这些设备上增加USB 3.0接口的数量。当连接到兼容的USB 3.0外设时，μPD720201和μPD720202能够实现高达5 Gbps的数据传输速率，这显著提高了数据交换的效率。 USB 3.0标准包括多种功能，如全双工通信、更高的带宽、多任务处理能力和更高的电源效率。xHCI接口提供了一种灵活的方式来管理和控制多个USB设备，同时保证了系统的稳定性和性能一致性。通过使用μPD720201或μPD720202，设计者可以构建出响应速度更快、连接更为顺畅的设备，适应不断增长的USB设备市场需求，如高速存储、视频传输和多媒体设备等。值得注意的是，为了确保兼容性和稳定性，这些控制器集成了必要的错误检测和恢复机制，以及高级电源管理技术，以优化电池寿命对于移动设备用户来说尤为重要。此外，它们还支持多种USB功能，如USB suspend（休眠）和resume（唤醒）模式，以及USB设备的分类和配置，这使得设备在不同应用场景下都能高效运作。 μPD720201和μPD720202作为先进的USB 3.0解决方案，不仅提供了高速数据传输，还为系统设计者带来了易用性和低功耗的优势，是现代电子设备设计中的关键组件。

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PD720201/

PD720202 2. PIN FUNCTION

R19DS0047EJ0500 Rev. 5.00 Page 8 of 40

Jan. 17, 2013

2.3.1 System Interface signal

Table 2-4. System Interface Signal

Pin Name 720201

Pin No.

720202

Pin No.

I/O

Type

Active

Level

Function

PONRSTB 14 11 I

(3.3 V

Schmitt

Input)

Low Power on reset signal. When supporting wakeup

from D3cold, this signal should be pulled high

with system auxiliary power supply.

SMIB 1 46 O

(Open

Drain)

Low System management Interrupt signal. This is

controlled with the USB Legacy Support

Control/Status register. Refer to the User’s

Manual.

2.3.2 PCI Express Interface

Table 2-5. PCI Express Interface

Pin Name 720201

Pin No.

720202

Pin No.

I/O

Type

Active

Level

Function

PECLKP 4 1 I

(PCIE)

−

PCI Express 100 MHz Reference Clock.

PECLKN 5 2 I

(PCIE)

−

PCI Express 100 MHz Reference Clock.

PETXP 7 4 O

(PCIE)

−

PCI Express Transmit Data+.

PETXN 8 5 O

(PCIE)

−

PCI Express Transmit Data-.

PERXP 10 7 I

(PCIE)

−

PCI Express Receive Data+.

PERXN 11 8 I

(PCIE)

−

PCI Express Receive Data-.

PERSTB 2 47 I

(3.3 V

Input)

Low PCI Express “PERST#” signal.

PEWAKEB 3 48 O

(Open

Drain)

Low PCI Express “WAKE#” signal. This signal is used

for remote wakeup mechanism, and requests the

recovery of power and reference clock input.

PECREQB 13 10 O

(Open

Drain)

Low PCI Express “CLKREQ#” signal. This signal is

used to request run/stop of reference clock.

PD720201/

PD720202 2. PIN FUNCTION

R19DS0047EJ0500 Rev. 5.00 Page 9 of 40

Jan. 17, 2013

2.3.3 USB Interface

Table 2-6. USB Interface

Pin Name 720201

Pin No.

720202

Pin No.

I/O

Type

Active

Level

Function

U3TXDP1 35 28 O

(USB3)

−

USB3.0 Transmit data D+ signal for SuperSpeed

U3TXDN1 36 29 O

(USB3)

−

USB3.0 Transmit data D- signal for SuperSpeed

U3RXDP1 38 31 I

(USB3)

−

USB3.0 Receive data D+ signal for SuperSpeed

U3RXDN1 39 32 I

(USB3)

−

USB3.0 Receive data D- signal for SuperSpeed

U2DP1 41 35 I/O

(USB2)

−

USB2.0 D+ signal for Hi-/Full-/Low-Speed

U2DM1 42 36 I/O

(USB2)

−

USB2.0 D− signal for Hi-/Full-/Low-Speed

OCI1B 26 19 I

(3.3 V

Input)

Low Over-current status input signal.

0: Over-current condition is detected

1: No over-current condition is detected

PPON1 27 20 O

(3.3 V

Output)

High USB port power supply control signal.

0: Power supply OFF

1: Power supply ON

U3TXDP2 44 37 O

(USB3)

−

USB3.0 Transmit data D+ signal for SuperSpeed

U3TXDN2 45 38 O

(USB3)

−

USB3.0 Transmit data D- signal for SuperSpeed

U3RXDP2 47 40 I

(USB3)

−

USB3.0 Receive data D+ signal for SuperSpeed

U3RXDN2 48 41 I

(USB3)

−

USB3.0 Receive data D- signal for SuperSpeed

U2DP2 50 44 I/O

(USB2)

−

USB2.0 D+ signal for Hi-/Full-/Low-Speed

U2DM2 51 45 I/O

(USB2)

−

USB2.0 D− signal for Hi-/Full-/Low-Speed

OCI2B 24 17 I

(3.3 V

Input)

Low Over-current status input signal.

0: Over-current condition is detected

1: No over-current condition is detected

PPON2 25 18 O

(3.3 V

Output)

High USB port power supply control signal.

0: Power supply OFF

1: Power supply ON

剩余42页未读，继续阅读

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