STM32F10xc系列高性能ARM Cortex-M3 MCU技术详解

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"STM32F10xc芯片手册是一份详细介绍STM32F101xC、STM32F101xD以及STM32F101xE系列芯片特性和应用的文档，包含了丰富的技术参数和使用指南。" STM32F10xc系列是基于ARM Cortex-M3内核的高性能、高密度访问线32位微控制器，主要特点包括： 1. **核心性能**：搭载32位Cortex-M3 CPU，最高运行频率可达36MHz，提供1.25 DMIPS/MHz（Dhrystone 2.1）的性能。CPU支持单周期乘法和硬件除法操作，显著提高了计算效率。 2. **内存配置**：包含256KB到512KB的闪存（Flash）存储空间，以及最多48KB的SRAM。此外，集成的静态存储器控制器支持4个片选，可兼容CompactFlash、SRAM、PSRAM、NOR和NAND等多种类型的外部存储器。同时，具备LCD并行接口，支持8080和6800模式。 3. **时钟与电源管理**：芯片工作电压范围为2.0V至3.6V，具备上电复位（POR）、掉电复位（PDR）和可编程电压检测器（PVD）。配备了4至16MHz的晶体振荡器、8MHz的工厂校准内部RC振荡器和40kHz的可校准内部RC振荡器，以及专为RTC和备份寄存器设计的32kHz振荡器。 4. **低功耗模式**：设计有睡眠、停止和待机等低功耗模式，以及VBAT供电，可以支持RTC和备份寄存器在低电压环境下正常工作。 5. **模拟特性**：内置1个12位的A/D转换器，最快转换速度为1μs，可连接多达16个通道，测量范围0至3.6V，还包含温度传感器。此外，有两个12位的D/A转换器，用于数字信号到模拟信号的转换。 6. **数据传输**：支持12通道的DMA（直接存储器访问），能够高效处理大量的数据传输任务，减轻CPU负担。这些特性使得STM32F10xc系列微控制器适用于多种嵌入式应用，如工业控制、物联网设备、智能家居、电机控制、传感器接口等场合。通过灵活的外设组合和强大的处理能力，开发者可以构建出高效、可靠的系统解决方案。

Description STM32F101xC, STM32F101xD, STM32F101xE

16/112 Doc ID 14610 Rev 8

2.3.7 Nested vectored interrupt controller (NVIC)

The STM32F101xC, STM32F101xD and STM32F101xE access line embeds a nested

vectored interrupt controller able to handle up to 60 maskable interrupt channels (not

including the 16 interrupt lines of Cortex™-M3) and 16 priority levels.

● Closely coupled NVIC gives low-latency interrupt processing

● Interrupt entry vector table address passed directly to the core

● Closely coupled NVIC core interface

● Allows early processing of interrupts

● Processing of late arriving higher priority interrupts

● Support for tail-chaining

● Processor state automatically saved

● Interrupt entry restored on interrupt exit with no instruction overhead

This hardware block provides flexible interrupt management features with minimal interrupt

latency.

2.3.8 External interrupt/event controller (EXTI)

The external interrupt/event controller consists of 19 edge detector lines used to generate

interrupt/event requests. Each line can be independently configured to select the trigger

event (rising edge, falling edge, both) and can be masked independently. A pending register

maintains the status of the interrupt requests. The EXTI can detect an external line with a

pulse width shorter than the Internal APB2 clock period. Up to 112 GPIOs can be connected

to the 16 external interrupt lines.

2.3.9 Clocks and startup

System clock selection is performed on startup, however the internal RC 8 MHz oscillator is

selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in

which case it is monitored for failure. If failure is detected, the system automatically switches

back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full

interrupt management of the PLL clock is available when necessary (for example with failure

of an indirectly used external oscillator).

Several prescalers are used to configure the AHB frequency, the high-speed APB (APB2)

domain and the low-speed APB (APB1) domain. The maximum frequency of the AHB and

APB domains is 36 MHz. See Figure 2 for details on the clock tree.

2.3.10 Boot modes

At startup, boot pins are used to select one of three boot options:

● Boot from user Flash: you have an option to boot from any of two memory banks. By

default, boot from Flash memory bank 1 is selected. You can choose to boot from Flash

memory bank 2 by setting a bit in the option bytes.

● Boot from system memory

● Boot from embedded SRAM

The bootloader is located in system memory. It is used to reprogram the Flash memory by

using USART1.

STM32F101xC, STM32F101xD, STM32F101xE Description

Doc ID 14610 Rev 8 17/112

2.3.11 Power supply schemes

● V

= 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.

Provided externally through V

pins.

● V

SSA

, V

DDA

= 2.0 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks,

RCs and PLL (minimum voltage to be applied to V

DDA

is 2.4 V when the ADC or DAC is

used). V

DDA

and V

SSA

must be connected to V

and V

, respectively.

● V

BAT

= 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup

registers (through power switch) when V

is not present.

For more details on how to connect power pins, refer to Figure 9: Power supply scheme.

2.3.12 Power supply supervisor

The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is

always active, and ensures proper operation starting from/down to 2 V. The device remains

in reset mode when V

is below a specified threshold, V

POR/PDR

, without the need for an

external reset circuit.

The device features an embedded programmable voltage detector (PVD) that monitors the

DDA

power supply and compares it to the V

PVD

threshold. An interrupt can be

generated when V

DDA

drops below the V

PVD

threshold and/or when V

DDA

is higher

than the V

PVD

threshold. The interrupt service routine can then generate a warning

message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to

Table 12: Embedded reset and power control block characteristics for the values of

POR/PDR

and V

PVD

2.3.13 Voltage regulator

The regulator has three operation modes: main (MR), low power (LPR) and power down.

● MR is used in the nominal regulation mode (Run)

● LPR is used in the Stop modes.

● Power down is used in Standby mode: the regulator output is in high impedance: the

kernel circuitry is powered down, inducing zero consumption (but the contents of the

registers and SRAM are lost)

This regulator is always enabled after reset. It is disabled in Standby mode.

2.3.14 Low-power modes

The STM32F101xC, STM32F101xD and STM32F101xE access line supports three low-

power modes to achieve the best compromise between low power consumption, short

startup time and available wakeup sources:

● Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can

wake up the CPU when an interrupt/event occurs.

● Stop mode

Stop mode achieves the lowest power consumption while retaining the content of

SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC

and the HSE crystal oscillators are disabled. The voltage regulator can also be put

either in normal or in low power mode.

Description STM32F101xC, STM32F101xD, STM32F101xE

18/112 Doc ID 14610 Rev 8

The device can be woken up from Stop mode by any of the EXTI line. The EXTI line

source can be one of the 16 external lines, the PVD output or the RTC alarm.

● Standby mode

The Standby mode is used to achieve the lowest power consumption. The internal

voltage regulator is switched off so that the entire 1.8 V domain is powered off. The

PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering

Standby mode, SRAM and register contents are lost except for registers in the Backup

domain and Standby circuitry.

The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a

rising edge on the WKUP pin, or an RTC alarm occurs.

Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop

or Standby mode.

2.3.15 DMA

The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for

DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-

peripheral transfers.

The two DMA controllers support circular buffer management, removing the need for user

code intervention when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with support for software

trigger on each channel. Configuration is made by software and transfer sizes between

source and destination are independent.

DMA can be used with the main peripherals: SPI, I

C, USART, general-purpose and basic

timers TIMx, DAC and ADC.

2.3.16 RTC (real-time clock) and backup registers

The RTC and the backup registers are supplied through a switch that takes power either on

supply when present or through the V

BAT

pin. The backup registers are forty-two 16-bit

registers used to store 84 bytes of user application data when V

power is not present.

They are not reset by a system or power reset, and they are not reset when the device

wakes up from the Standby mode.

The real-time clock provides a set of continuously running counters which can be used with

suitable software to provide a clock calendar function, and provides an alarm interrupt and a

periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the

internal low power RC oscillator or the high speed external clock divided by 128. The

internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using

an external 512 Hz output to compensate for any natural quartz deviation. The RTC features

a 32-bit programmable counter for long term measurement using the Compare register to

generate an alarm. A 20-bit prescaler is used for the time base clock and is by default

configured to generate a time base of 1 second from a clock at 32.768 kHz.

2.3.17 Timers and watchdogs

The high-density STM32F101xx access line devices include up to four general-purpose

timers, two basic timers, two watchdog timers and a SysTick timer.

Table 4 compares the features of the general-purpose and basic timers.

STM32F101xC, STM32F101xD, STM32F101xE Description

Doc ID 14610 Rev 8 19/112

General-purpose timers (TIMx)

There are up to 4 synchronizable general-purpose timers (TIM2, TIM3, TIM4 and TIM5)

embedded in the STM32F101xC, STM32F101xD and STM32F101xE access line devices.

These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and

feature 4 independent channels each for input capture/output compare, PWM or one-pulse

mode output. This gives up to 16 input captures / output compares / PWMs on the largest

packages.

The general-purpose timers can work together with the advanced-control timer via the Timer

Link feature for synchronization or event chaining. Their counter can be frozen in debug

mode. Any of the general-purpose timers can be used to generate PWM outputs. They all

have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

Basic timers TIM6 and TIM7

These timers are mainly used for DAC trigger generation. They can also be used as a

generic 16-bit time base.

Independent watchdog

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free running timer for application timeout

management. It is hardware or software configurable through the option bytes. The counter

can be frozen in debug mode.

Window watchdog

The window watchdog is based on a 7-bit downcounter that can be set as free running. It

can be used as a watchdog to reset the device when a problem occurs. It is clocked from the

main clock. It has an early warning interrupt capability and the counter can be frozen in

debug mode.

Table 4. Timer feature comparison

Timer

Counter

resolution

Counter

type

Prescaler

factor

DMA request

generation

Capture/compare

channels

Complementary

outputs

TIM2,

TIM3,

TIM4,

TIM5

16-bit

Up,

down,

up/down

Any integer

between 1

and 65536

Ye s 4 N o

TIM6,

TIM7

16-bit Up

Any integer

between 1

and 65536

Ye s 0 N o

Description STM32F101xC, STM32F101xD, STM32F101xE

20/112 Doc ID 14610 Rev 8

SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard

down counter. It features:

● A 24-bit down counter

● Autoreload capability

● Maskable system interrupt generation when the counter reaches 0.

● Programmable clock source

2.3.18 I²C bus

Up to two I²C bus interfaces can operate in multi-master and slave modes. They support

standard and fast modes.

They support 7/10-bit addressing mode and 7-bit dual addressing mode (as slave). A

hardware CRC generation/verification is embedded.

They can be served by DMA and they support SMBus 2.0/PMBus.

2.3.19 Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F101xC, STM32F101xD and STM32F101xE access line embeds three

universal synchronous/asynchronous receiver transmitters (USART1, USART2 and

USART3) and two universal asynchronous receiver transmitters (UART4 and UART5).

These five interfaces provide asynchronous communication, IrDA SIR ENDEC support,

multiprocessor communication mode, single-wire half-duplex communication mode and

have LIN Master/Slave capability. The five interfaces are able to communicate at speeds of

up to 2.25 Mbit/s.

USART1, USART2 and USART3 also provide hardware management of the CTS and RTS

signals, Smart Card mode (ISO 7816 compliant) and SPI-like communication capability. All

interfaces can be served by the DMA controller except for UART5.

2.3.20 Serial peripheral interface (SPI)

Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in

full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode

frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC

generation/verification supports basic SD Card/MMC modes.

All SPIs can be served by the DMA controller.

2.3.21 GPIOs (general-purpose inputs/outputs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current-

capable except for analog inputs.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

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