Xilinx Virtex-7 FPGA Gen3 PCIe Core 设计指南

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"Xilinx PCIe IP-Core文档，详细介绍了在Virtex-7 FPGA上使用的Gen3 Integrated Block for PCI Express v3.0，适用于Vivado Design Suite。" 本文档是Xilinx公司关于其Virtex-7 FPGA上的PCI Express (PCIe) Gen3 Integrated Block的LogiCORE IP产品指南，版本号PG023，发布于2014年11月19日。该IP核是针对高速、高带宽通信设计的关键组件，旨在实现FPGA与基于PCIe标准的外部设备之间的高效数据传输。 **1. IP事实** 章节概述了IP核的关键特性，包括它支持的应用（如高性能计算、网络、存储等）以及不支持的功能。同时，它提供了关于许可和订购的信息，帮助用户了解如何获得和使用该IP核。 **2. 产品规格** 这一章详细描述了IP核的合规性标准，如符合PCI Express v3.0规范。它还涵盖了资源利用率，帮助设计师了解在FPGA中集成IP核时所需的逻辑资源。此外，它讨论了选择不同配置块的指导原则，端口描述，以及各种属性的描述。配置空间的部分详细列出了用于控制和配置PCIe接口的寄存器。 **3. 设计指南** 本章为使用该IP核进行系统设计提供了总体指导，包括系统时钟的要求和设置。时钟需求部分强调了正确时序的重要性，而重置信号的处理则确保了系统的稳定初始化。共享逻辑部分讨论了在设计中如何有效地利用共享资源。AXI4-Stream接口的描述解释了如何通过这个接口进行数据传输，以及其操作流程。电源管理部分涵盖了节能特性和中断请求的生成机制。配置空间寄存器和配置接口的使用方法帮助用户理解和控制PCIe链接的状态。 **4. 设计流程步骤** 这一章详细阐述了从自定义设计到实现的整个流程，包括如何配置和优化IP核以适应特定应用，链接训练（针对2、4和8条lane的组件），lane反转功能，以及串联配置方式。最后，章节还列出了一些已知的设计限制，以帮助开发者避免潜在问题。 Xilinx PCIe Gen3 Integrated Block提供了一套全面的解决方案，用于在Virtex-7 FPGA平台上实现高效、可靠的PCIe v3.0接口。这份产品指南是开发人员进行高速接口设计的重要参考资料，涵盖了从设计概念到实现的每一个关键步骤。

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PG023 November 19, 2014

Chapter 2: Product Specification

Table 2-5: Sideband Signal Descriptions in m_axis_cq_tuser

Bit Index Name Width Description

3:0 first_be[3:0] 4

Byte enables for the first Dword of the payload.

This field reflects the setting of the First_BE bits in the

Transaction-Layer header of the TLP. For Memory Reads

and I/O Reads, these four bits indicate the valid bytes to

be read in the first Dword. For Memory Writes and I/O

Writes, these bits indicate the valid bytes in the first

Dword of the payload. For Atomic Operations and

Messages with a payload, these bits are set to all 1s.

This field is valid in the first beat of a packet, that is,

when sop and m_axis_cq_tvalid are both High.

7:4 last_be[3:0] 4

Byte enables for the last Dword.

This field reflects the setting of the Last_BE bits in the

Transaction-Layer header of the TLP. For Memory Reads,

these four bits indicate the valid bytes to be read in the

last Dword of the block of data. For Memory Writes,

these bits indicate the valid bytes in the ending Dword

of the payload. For Atomic Operations and Messages

with a payload, these bits are set to all 1s.

This field is valid in the first beat of a packet, that is,

when sop and m_axis_cq_tvalid are both High.

39:8 byte_en[31:0] 32

The user logic can optionally use these byte enable bits

to determine the valid bytes in the payload of a packet

being transferred. The assertion of bit i of this bus

during a transfer indicates to the user application that

byte i of the m_axis_cq_tdata bus contains a valid

payload byte. This bit is not asserted for descriptor

bytes.

Although the byte enables can be generated by user

logic from information in the request descriptor

(address and length) as well as the settings of the

first_be and last_be signals, the user application

has the option to use these signals directly instead of

generating them from other interface signals.

When the payload size is more than two Dwords (eight

bytes), the one bit on this bus for the payload is always

contiguous. When the payload size is two Dwords or

less, the one bit can be non-contiguous.

For the special case of a zero-length memory write

transaction defined by the PCI Express specifications,

the byte_en bits are all 0s when the associated

one-DW payload is being transferred.

Bits [31:16] of this bus are set permanently to 0 by the

core when the interface width is configured as 128 bits,

and bits [31:8] are set permanently to 0 when the

interface width is configured as 64 bits.

40 sop 1

Start of packet.

This signal is asserted by the core in the first beat of a

packet to indicate the start of the packet. Use of this

signal is optional.

Send Feedback

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PG023 November 19, 2014

Chapter 2: Product Specification

Completer Completion (CC) Interface

The Completer Completion (CC) interface is used by the user application to transmit the

completer requests. You can process all Non-Posted transactions as split transactions. That

is, it can continue to accept new requests on the Completer Request (CQ) interface while

sending a completion for a request.

Tabl e 2-6 defines the ports in the CC interface of the core. In the Width column, DW

denotes the configured data bus width (64, 128, or 256 bits).

41 discontinue 1

This signal is asserted by the core in the last beat of a

TLP, if it has detected an uncorrectable error while

reading the TLP payload from its internal FIFO memory.

The user application must discard the entire TLP when

such an error is signaled by the core.

This signal is never asserted when the TLP has no

payload. It is asserted only in a cycle when

m_axis_cq_tlast is High.

When the core is configured as an Endpoint, the error is

also reported by the core to the Root Complex to which

it is attached, using Advanced Error Reporting (AER).

42 tph_present 1

This bit indicates the presence of a Transaction

Processing Hint (TPH) in the request TLP being

delivered across the interface. This bit is valid when sop

and m_axis_cq_tvalid are both High.

44:43 tph_type[1:0] 2

When a TPH is present in the request TLP, these two bits

provide the value of the PH[1:0] field associated with

the hint. These bits are valid when sop and

m_axis_cq_tvalid are both High.

52:45 tph_st_tag[7:0] 8

When a TPH is present in the request TLP, this output

provides the 8-bit Steering Tag associated with the hint.

These bits are valid when sop and

m_axis_cq_tvalid are both High.

84:53 parity 32

Odd parity for the 256-bit transmit data. Bit i provides

the odd parity computed for byte i of

m_axis_cq_tdata. Only the lower 16 bits are to be

used when the interface width is 128 bits, and only the

lower 8 bits are to be used when the interface width is

64 bits. Bits [31:16] are set permanently to 0 by the core

when the interface width is configured as 128 bits, and

bits [31:8] are set permanently to 0 when the interface

width is configured as 64 bits.

Table 2-5: Sideband Signal Descriptions in m_axis_cq_tuser (Cont’d)

Bit Index Name Width Description

Send Feedback

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PG023 November 19, 2014

Chapter 2: Product Specification

Table 2-6: CC Interface Port Descriptions

Port Direction Width Description

s_axis_cc_tdata Input DW

Completer Completion Data bus.

Completion data from the user application to the core. Only

the lower 128 bits are to be used when the interface width is

128 bits, and only the lower 64 bits are to be used when the

interface width is 64 bits.

s_axis_cc_tuser Input 33

Completer Completion User Data.

This set of signals contain sideband information for the TLP

being transferred. These signals are valid when

s_axis_cc_tvalid is High.

Table 2-7, pag e 19 describes the individual signals in this

set.

s_axis_cc_tlast Input 1

TLAST indication for Completer Completion Data.

The user application must assert this signal in the last cycle

of a packet to indicate the end of the packet. When the TLP

is transferred in a single beat, the user application must set

this bit in the first cycle of the transfer.

s_axis_cc_tkeep Input DW/32

TKEEP indication for Completer Completion Data.

The assertion of bit i of this bus during a transfer indicates

to the core that Dword i of the s_axis_cc_tdata bus

contains valid data. The user application must set this bit to

1 contiguously for all Dwords starting from the first Dword

of the descriptor to the last Dword of the payload. Thus,

s_axis_cc_tdata must be set to all 1s in all beats of a

packet, except in the final beat when the total size of the

packet is not a multiple of the width of the data bus (both in

Dwords). This is true for both Dword-aligned and

address-aligned modes of payload transfer.

Bits [7:4] of this bus are not used by the core when the

interface width is configured as 128 bits, and bits [7:2] are

not used when the interface width is configured as 64 bits.

s_axis_cc_tvalid Input 1

Completer Completion Data Valid.

The user application must assert this output whenever it is

driving valid data on the s_axis_cc_tdata bus. The user

application must keep the valid signal asserted during the

transfer of a packet. The core paces the data transfer using

the s_axis_cc_tready signal.

s_axis_cc_tready Output 4

Completer Completion Data Ready.

Activation of this signal by the core indicates that it is ready

to accept data. Data is transferred across the interface when

both s_axis_cc_tvalid and s_axis_cc_tready are

asserted in the same cycle.

If the core deasserts the ready signal when the valid

signal is High, the user application must maintain the data

on the bus and keep the valid signal asserted until the core

has asserted the ready signal.

Send Feedback

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PG023 November 19, 2014

Chapter 2: Product Specification

Requester reQuest (RQ) Interface

The Requester reQuest (RQ) interface is used by the user application to generate requests

to remote PCIe® devices. Ta ble 2-8 defines the ports in the RQ interface of the core. In the

Width column, DW denotes the configured data bus width (64, 128, or 256 bits).

Table 2-7: Sideband Signal Descriptions in s_axis_cc_tuser

Bit Index Name Width Description

0 discontinue 1

This signal can be asserted by the user application during

a transfer if it has detected an error (such as an

uncorrectable ECC error while reading the payload from

memory) in the data being transferred and desires to

abort the packet. The core nullifies the corresponding TLP

on the link to avoid data corruption.

The user application can assert this signal during any

cycle during the transfer. It can either choose to terminate

the packet prematurely in the cycle where the error was

signaled, or can continue until all bytes of the payload are

delivered to the core. In the latter case, the core treats the

error as sticky for the following beats of the packet, even

if the user application deasserts the discontinue signal

before the end of the packet.

The discontinue signal can be asserted only when

s_axis_cc_tvalid is High. The core samples this

signal only when s_axis_cc_tready is High. Thus,

when asserted, it should not be deasserted until

s_axis_cc_tready is High.

Discontinue is not supported for Non Posted TLPs.

The client can assert this signal in any cycle except the

first cycle during the transfer.

When the core is configured as an Endpoint, this error is

also reported by the core to the Root Complex to which it

is attached, using AER.

32:1 parity 32

Odd parity for the 256-bit data.

When parity checking is enabled in the core, user logic

must set bit i of this bus to the odd parity computed for

byte i of s_axis_cc_tdata. Only the lower 16 bits are

to be used when the interface width is 128 bits, and only

the lower 8 bits are to be used when the interface width is

64 bits.

When an interface parity error is detected, it is recorded

as an uncorrectable internal error and the packet is

discarded. According to the Base Spec 6.2.9, an

uncorrectable internal error is an error that occurs within a

component that results in improper operation of the

component. The only method of recovering from an

uncorrectable internal error is reset or hardware

replacement.

The parity bits can be permanently tied to 0 if parity check

is not enabled in the core.

Send Feedback

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PG023 November 19, 2014

Chapter 2: Product Specification

Table 2-8: RQ Interface Port Descriptions

Port Direction Width Description

s_axis_rq_tdata Input DW

Requester reQuest Data bus.

This input contains the requester-side request data from the

user application to the core. Only the lower 128 bits are to be

used when the interface width is 128 bits, and only the lower

64 bits are to be used when the interface width is 64 bits.

s_axis_rq_tuser Input 60

Requester reQuest User Data.

This set of signals contains sideband information for the TLP

being transferred. These signals are valid when

s_axis_rq_tvalid is High.

Table 2-9, pag e 22 describes the individual signals in this set.

s_axis_rq_tlast Input 1

TLAST Indication for Requester reQuest Data.

The user application must assert this signal in the last cycle of

a TLP to indicate the end of the packet. When the TLP is

transferred in a single beat, the user application must set this

bit in the first cycle of the transfer.

s_axis_rq_tkeep Input DW/32

TKEEP Indication for Requester reQuest Data.

The assertion of bit i of this bus during a transfer indicates to

the core that Dword i of the s_axis_rq_tdata bus contains

valid data. The user application must set this bit to 1

contiguously for all Dwords, starting from the first Dword of

the descriptor to the last Dword of the payload. Thus,

s_axis_rq_tdata must be set to all 1s in all beats of a

packet, except in the final beat when the total size of the

packet is not a multiple of the width of the data bus (both in

Dwords). This is true for both Dword-aligned and

address-aligned modes of payload transfer.

Bits [7:4] of this bus are not used by the core when the interface

width is configured as 128 bits, and bits [7:2] are not used when

the interface width is configured as 64 bits.

s_axis_rq_tready Output 4

Requester reQuest Data Ready.

Activation of this signal by the core indicates that it is ready to

accept data. Data is transferred across the interface when both

s_axis_rq_tvalid and s_axis_rq_tready are asserted

in the same cycle.

If the core deasserts the ready signal when the valid signal

is High, the user application must maintain the data on the bus

and keep the valid signal asserted until the core has asserted

the ready signal.

You can check all 4 bits to 1 or 0.

s_axis_rq_tvalid Input 1

Requester reQuest Data Valid.

The user application must assert this output whenever it is

driving valid data on the s_axis_rq_tdata bus. The user

application must keep the valid signal asserted during the

transfer of a packet. The core paces the data transfer using the

s_axis_rq_tready signal.

Send Feedback

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