"USB 2.0 UTMI协议及接口英文版详解与规范"

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The "USB 2.0 Transceiver Macrocell Interface (UTMI) Specification Version 1.05" is a document released by Intel Corporation in 2001. It includes the USB2.0 UTMI protocol in English as well as the USB2.0 UTM interface in English. The document spans 66 pages and is intended to provide a detailed and technical specification for the USB 2.0 Transceiver Macrocell. The specification contains important copyright information, noting that it is the intellectual property of Intel Corporation and is provided "as is" with no warranties whatsoever, including any warranty of merchantability or fitness for any particular purpose. It also includes a contact email address for sending comments and feedback. Intel Corporation holds all rights to the document, and it is clear that the information contained within is valuable and proprietary. The specification likely contains detailed technical information regarding the USB 2.0 Transceiver Macrocell, including its design, functionality, and interface specifications. The release date of the document, March 29, 2001, indicates that it is based on the USB 2.0 standard, which was a significant advancement in data transfer technology at the time. The inclusion of the UTMI protocol and UTM interface in English suggests that the document is intended for a broad audience, including those who speak English as a first or second language. Overall, the "USB 2.0 Transceiver Macrocell Interface (UTMI) Specification Version 1.05" is a comprehensive and technical document released by Intel Corporation. It provides detailed information about the USB 2.0 Transceiver Macrocell and is a valuable resource for individuals and organizations involved in the development and implementation of USB 2.0 technology.

USB2.0 Transceiver Macrocell

4 UTMI Signal Descriptions

4.1 System Interface Signals

Table 1: System Interface Signals

Name Direction

Active

Level

Description

CLK Output Rising-

Edge

Clock. This output is used for clocking receive and

transmit parallel data.

60 MHz HS/FS, with 8-bit interface

30 MHz HS/FS, with 16-bit interface

48 MHz FS Only, with 8-bit interface

6 MHz LS Only, with 8-bit interface

See section 4.1.1 for more information on CLK.

Reset Input High

Reset. Reset all state machines in the UTM.

Xcvr

Select

Input N/A

Transceiver Select. This signal selects between the FS

and HS transceivers:

0: HS transceiver enabled

1: FS transceiver enabled

This signal is not provided in FS Only and LS Only

transceiver implementations.

See section 4.1.2 for more information on XcvrSelect.

Term

Select

Input N/A

Termination Select. This signal selects between the FS

and HS terminations:

0: HS termination enabled

1: FS termination enabled

This signal is not provided in FS Only and LS Only

transceiver implementations.

See section 4.1.3 for more information on TermSelect.

SuspendM Input Low

Suspend. Places the Macrocell in a mode that draws

minimal power from supplies. Shuts down all blocks not

necessary for Suspend/Resume operation. While

suspended, TermSelect must always be in FS mode to

ensure that the 1.5K pull-up on DP remains powered.

0: Macrocell circuitry drawing suspend current

1: Macrocell circuitry drawing normal current

LineState

(0-1)

Output N/A

Line State. These signals reflect the current state of the

single ended receivers. They are combinatorial until a

"usable" CLK is available then they are synchronized to

CLK. They directly reflect the current state of the DP

(LineState[0]) and DM (LineState[1]) signals:

DM DP Description

0 0 0: SE0

0 1 1: 'J' State

1 0 2: 'K' State

1 1 3: SE1

See section 4.1.4 for more information on LineState.

USB2.0 Transceiver Macrocell

OpMode

(0-1)

Input N/A

Operational Mode. These signals select between

various operational modes:

[1] [0] Description

0 0 0: Normal Operation

0 1 1: Non-Driving

1 0 2: Disable Bit Stuffing and NRZI encoding

1 1 3: Reserved

4.1.1 CLK

Nominal CLK accuracy is ±500ppm for frequency, and 50±5% duty cycle.

No transitions of CLK should occur until it is "usable", where usable is defined as a frequency accuracy of

±10%, and a duty cycle accuracy of 50±10%.

Conceptually, there is a "CLKUsable" signal, internal to the UTM, which blocks any transitions of CLK

until it is "usable". This "CLKUsable" signal is also used to switch the LineState output between CLK

synchronized and combinatorial signaling. See section 5.22.2.3 for further discussion of CLK.

4.1.1.1 Options

There are 3 possible implementations for a UTMI device: HS/FS, FS Only, or LS Only. The HS/FS version

has 4 interface options: 16-bit unidirectional, 8-bit unidirectional, 16-bit bidirectional/8-bit unidirectional,

and 8-bit bi-directional. In each case, when a 16-bit option is selected CLK is at 30 MHz, and when an 8-bit

option is selected CLK is at 60 MHz.

Note that the 16-bit bidirectional/8-bit unidirectional uses the "DataBus16_8" signal to swtich between

them. This signal also switches the CLK frequency.

The FS Only, or LS Only implementations only support 48 MHz and 6 MHz clocks, respectively, and

always use 8 bit interfaces (either 8-bit unidirectional or 8-bit bi-directional).

4.1.2 XcvrSelect

XcvrSelect controls a number of transceiver related elements, for instance.

• Selects the receiver (source for the Mux block) in the receive data path.

• It is used as a gating term for enabling the respective HS or FS Transmit Driver.

• Switch internal UTM clocks to shared logic.

4.1.3 TermSelect

TermSelect controls a number of termination related elements, for instance.

• In HS mode the FS Driver is forced to assert an SE0 on the USB, providing the 50 Ohm termination to

ground and generating the HS Idle state on the bus.

• In FS Mode TermSelect enables the 1.5K pull-up on to the DP signal to generate the FS Idle state on

the bus.

4.1.4 LineState

The LineState signals are used by the SIE for detecting reset, speed signaling, packet timing, and to

transition from one behavior to another.

Note: While data packets are being transmitted or received on the USB the LineState signals may toggle

randomly between the 'J' and 'K' states in FS, and remain in the ‘J’ state in HS. The SIE should

ignore these transitions.

4.1.4.1 Synchronization

To minimize unwanted transitions to the SIE during normal operation, the LineState is internally

synchronized with CLK. When synchronized, the setup and hold timing of LineState is identical to

DataOut. The exception to this is when CLK is not "usable". If CLK is not "usable" then the LineState

USB2.0 Transceiver Macrocell

signals are not synchronized, but driven with combinatorial logic directly from the DP and DM signal

lines. The UTM must multiplex between combinatorial and synchronous LineState output depending on

whether CLK is "usable". See section 4.1.1 for a discussion of what a "usable" CLK is. See section 4.1.4.3

for an addition method of minimizing LineState transitions in HS mode.

4.1.4.2 Signaling Levels

The voltage thresholds that the LineState signals use for comparison on DP and DM depend on the state of

XcvrSelect. LineState uses HS thresholds when the HS transceiver is enabled (XcvrSelect = 0) and FS

thresholds when the FS transceiver is enabled (XcvrSelect = 1). FS Only and LS Only implementations

always use FS thresholds. See first paragraph of section 5.22 for more details.

There is no concept of variable, single ended thresholds in the USB 2.0 specification. The assumption (see

Figure 7-1 in the USB 2.0 spec) was that the HS receiver would be used to detect a Chirp K or J, where the

output of the HS receiver is always qualified with the "Squelch" signal. If Squelch = 1 then the output of

the HS receiver is meaningless.

In the macrocell, as an alternative to using variable thresholds for the single ended receivers the following

approach to encoding the LineState outputs can be used.

Mode

Full

Speed

High

Speed

Chirp Invalid

XcvrSelect

1 0 0 1

TermSelect

1 0 1 0

SE0 SE0 Squelch Squelch Invalid

J State J

!Squelch

! Squelch &

HS_Differential_Receiver_Output

Invalid

K State K Invalid

! Squelch &

! HS_Differential_Receiver_Output

Invalid

Line

State

SE1 SE1 Invalid Invalid Invalid

Note: With this scheme, SE1 is never generated in HS Mode. This is not a problem because SE1 is

defined as an illegal bus state in the USB 2.0 specification and is provided by the UTM for debug

purposes only.

Note: An SIE attached to a LS Only UTM implementation must interpret the K State as Bus Idle.

4.1.4.3 Minimizing Transitions

In HS mode, 3 ms of no USB activity (Idle state) signals a reset. The SIE monitors LineState for Idle

state

. If in HS mode, LineState is simply the output of the HS Differential receiver then LineState will

toggle randomly while packets are on the USB. To minimize transitions on LineState while in HS mode

the presence of Squelch can be used to force a LineState to a J State.

This scheme allows LineState to indicate a J State whenever a packet is on the USB, thus satisfying the

requirement that a LineState transition occurs when there is activity on the USB, while minimizing the

number of LineState transitions while there is data on the bus. Using TermSelect, rather than XcvrSelect,

allows the Speed Chirp protocol to complete before enabling this mode.

This approach has the side effect of turning any Chirp K's after the HS terminations are enabled

(TermSelect = 0. See Figure 25, T7 to T8) into Chirp J's. However, this only occurs after the SIE has

determined that it is attached to a HS downstream facing port and the SIE is no longer interested in whether

a J or K is on the bus.

Note: This term is optional. See section 4.1.4.3 for a discussion of this term.

Note: When identifying bus "activity", the SIE should not use the data path to monitor SOFs.

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