ZC706 PCIe Targeted Reference Design User Guide

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"UG963-ZC706-pci-trd-ug" 是一份针对Xilinx ZC706开发板的PCI Express（PCIe）目标参考设计用户指南，适用于Vivado Design Suite 2015.4版本。这份文档主要提供了关于如何在ZC706开发平台上进行PCIe设计的详细步骤和指导。 ZC706是Xilinx公司推出的一款基于Zynq-7000 All Programmable System-on-Chip (SoC)的高性能评估和开发平台。该开发板集成了ARM Cortex-A9双核处理器和可编程逻辑单元，支持多种高速接口，包括PCIe，用于高性能数据传输和系统扩展。 PCIe Targeted Reference Design (TRD) 是一套完整的参考设计，旨在帮助开发者快速理解和实现PCIe协议在FPGA中的应用。这份用户指南详细介绍了如何配置、综合、实现和测试ZC706上的PCIe接口，涵盖了从基础概念到实际操作的所有关键环节。用户指南内容可能包括但不限于以下几个方面： 1. **系统架构**：解释ZC706开发板的硬件结构，特别是PCIe接口的物理层（PHY）、协议层（Endpoint或Root Port）以及与其连接的主机系统的交互方式。 2. **设计流程**：介绍使用Vivado Design Suite进行PCIe设计的基本步骤，包括创建项目、导入IP核、配置PCIe接口参数、生成比特流（bitstream）等。 3. **IP核配置**：详细说明如何配置Xilinx提供的PCIe Core，包括速度等级、端点类型、中断处理、DMA机制等。 4. **硬件连接**：指导用户如何正确连接ZC706开发板到PCIe插槽，并提供必要的硬件接线图和电气规范。 5. **软件开发**：阐述如何编写驱动程序以与PCIe设备通信，可能包括Linux内核驱动的编写和用户空间应用的开发。 6. **测试与验证**：提供一系列测试用例和步骤，帮助用户验证PCIe设计的功能和性能，确保其符合PCI Express规范。 7. **故障排查**：列出常见的问题和解决方案，帮助开发者解决在设计和实现过程中遇到的问题。 8. **安全性和合规性**：提醒用户注意知识产权保护和合规性问题，例如遵守PCI-SIG（PCI Special Interest Group）的标准和规定。 9. **许可证和免责声明**：强调Xilinx提供的材料“按原样”提供，不提供任何明示或暗示的保修，包括但不限于适销性、非侵权或特定用途适用性的保修。同时，Xilinx对因使用这些材料而可能导致的任何损失或损害不承担责任。这份用户指南对于想要在ZC706开发板上实现PCIe功能的工程师来说是一份宝贵的资源，它能够帮助他们快速上手并有效避免在设计过程中遇到的常见问题。

ZC706 PCIe TRD User Guide www.xilinx.com 14

UG963 (v2015.4) January 19, 2016

Hardware Architecture

AXI master port (M_AXI_GP) - This AXI master port interfaces with AXI slave IPs in the PL

through an AXI-Lite interconnect. The CPU manages initializing and controlling the video

pipeline through this port.

Input/Output Peripherals

The input/output peripherals (IOP) unit includes communication peripherals. GPIO,

Ethernet, USB, I2C, and SD controllers from the PS are used extensively in this design.

GPIO - The 64-bit general purpose input/outputs (GPIOs) are connected to the PL through

the extendable multiplexed I/O (EMIO) interface. Sixty-four bits are divided into two banks,

each having 32 bits. Because each GPIO bit can be dynamically configured as input or

output, GPIO bits are used in this design for a variety of functions.

Memory Interfaces

The memory interfaces unit includes the DDR memory controller and nonvolatile memory

controllers. The DDR memory controller includes a 4-port arbiter. One AXI port is dedicated

for ARM CPU access and two ports are dedicated for high performance AXI interface master

devices in the programmable logic. The remaining port is shared by all other AXI masters. In

this design, DDR3 is configured to run at 533 MHz, and the AXI interface is running at 355

MHz.

PL Clocks

The PS provides four (FCLKCLK[3:0]) fully programmable clocks to the PL. These clocks are

routed directly to PL clock buffers to serve as a frequency source for the PL. The clock

generator module in PL gets a 100 MHz clock from FCLKCLK[0].

PL Reset

The PS provides four (FCLKRESETN[3:0]) fully programmable reset signals to the PL. These

signals are asynchronous to PS clocks. The PL logic reset block in this design receives input

from FCLKRESETN[0] and generates necessary reset signals for the design implemented in

PL.

Programmable Logic

The video IP and custom logic implemented is implemented in PL.

PCIe Endpoint Device

The Zynq-7000 ZC7Z045 AP SoC has a x4 Gen2 capable PCIe block. This block interfaces to

the root port in the host system and forms the basic communicating entity with the host.

The PCIe Endpoint block provides an AXI Stream compliant interface with 64-bit width

operating at 250 MHz.

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ZC706 PCIe TRD User Guide www.xilinx.com 17

UG963 (v2015.4) January 19, 2016

Hardware Architecture

AXI Interconnect

The PL design has two interconnects for AXI memory-mapped masters and one

interconnect for the AXI register interface. AXI memory-mapped interconnects are

connected to masters like AXI_VDMA and logiCVC-ML. Slaves connected to these

interconnects include HP0 and HP2 ports of the Zynq-7000 XC7Z045 AP Soc PS. This

interconnect operates at 150 MHz and the data width is 64-bits. The read/write acceptance

and issuance are set to 8 levels. The acceptance and issuance helps improve system

performance. The PS HP port can accept a maximum burst length of 16 levels. This imposes

a limitation on getting minimum acceptable bandwidth for every master in a multi-master

system. The optimum setting of issuance and acceptance reduces throttle on the bus and

compensates for long latencies. The AXI register interface is clocked at 75 MHz. The

XC7Z045 AP Soc GP0 port acts as master on this interconnect and connected slaves have

The operations of the video pipeline are controlled by registers inside every IP. Depending

upon data flow required in the video pipeline, the processor writes these registers through

the AXI-Lite interconnect. The AXI-Lite interconnect accepts write or read transfers from the

CPU, performs address decoding, selects a particular slave, and establishes a

communication channel between the CPU and the slave device.

AXI Video DMA

The AXI VDMA has an AXI streaming interface on one side and an AXI memory-mapped

interface on the other side. The VDMA has two channels: MM2S (memory-mapped to

streaming) and S2MM (streaming to memory-mapped). The MM2S channel reads the

number of data beats programmed through the C_MM2S_MAX_BURST_LENGTH parameter

and presents it to the slave device connected through the streaming interface. The data

width of the streaming interface can be different than the memory-mapped interface and

controlled through C_M_AXIS_MM2S_TDATA_WIDTH. The data width of the S2MM

memory-mapped interface is controlled by the C_M_AXI_MM2S_DATA_WIDTH parameter.

The S2MM channel receives data from the master device connected through the streaming

interface. The C_S_AXIS_S2MM_TDATA_WIDTH parameter decides the width of the

streaming interface. Data received on the streaming interface is then written into the

system memory through the memory-mapped interface. The C_M_AXI_S2MM_DATA_WIDTH

parameter decides the data width of the memory-mapped interface and

C_S2MM_MAX_BURST_LENGTH governs the burst length of the write transaction. In this

design, the streaming interface data width is set to 32-bits and the memory-mapped

interface is configured as 64-bits wide. The AXI VDMA is used in simple register direct

mode, which removes the area cost of the scatter-gather feature. Initialization, status, and

management registers in the AXI VDMA core are accessed through an AXI4-Lite slave

interface. To get the best possible throughput for AXI VDMA instances, the maximum burst

length is set to 16. In addition, the master interfaces have a read and write issuance of 8

levels and a read and write FIFO depth of 512 to maximize throughput. The line buffers

inside the AXI VDMA for the read and write sides are set to 4K deep and the store and

forward feature of the AXI VDMA are enabled on both channels to improve system

performance and reduce the risk of system throttling.

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